LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 346

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Note that if PAR finds timing preferences in the preference file, timing-driven placement and routing is automatically
invoked.
Timing Driven PAR Process
The ispLEVER software offers timing driven placement and routing through an integrated static timing analysis util-
ity (i.e., it does not depend on input stimulus to the circuit). This means that placement and routing is executed
according to timing constraints (preferences) that the designer specifies up front in the design process. PAR
attempts to meet timing constraints in the preference file without exceeding the specified timing constraints.
To use timing-driven PAR, the designer simply writes timing preferences into a preference (.prf) file, which serves
as input to the integrated static timing analysis utility. See the Process Flows section of the ispLEVER on-line help
system for more information about the PAR software and ispLEVER design flow.
General Strategy Guidelines
Preferences should be inserted at the front end of a design flow. This prevents designers from having to change
PAR physical preferences as net names may change with every synthesis run.
The tips below are general recommendations.
Typical Design Preferences
The full preference language includes many different design constraints from very global preferences to very spe-
cific preferences. To a new user this is a very large list to digest and utilize effectively. Listed here are the recom-
mended preferences that should be applied to all designs. Refer to the Constraints & Preferences section of the
ispLEVER on-line help system for more information on preferences.
• A faster cost-based cleanup routing, which makes routing decisions by assigning weighted values to the
• A more CPU-intensive, delay-based cleanup routing, which makes routing decisions based on computed
• Analyze Trace results in the integrated static timing analysis utility report (.twr) file carefully.
• Look at mapped frequency before you PAR a design to check for errors and warnings in the preference file
• Determine if design changes are required. A typical example design change is pipelining, or registering, the
• It is recommended to perform place and route early in the design phase with a preliminary preference file to
• Tune up your preference file to include all I/O and internal timing paths as appropriate. The Translating
• Establish the pin-out in the preference file. Locating I/O can also be done in the HDL, as well as in synthesis
• Push PAR when necessary by running multiple routing iterations and multiple placement iterations.
• Revise the preference file as appropriate, especially utilizing multicycle opportunities when possible.
• Floorplan the design if necessary (see technical note number TN1010, Lattice Semiconductor Design
• For Lattice Semiconductor ORCA Series devices, use clock boosting as a last resort, remembering to run
factors (for example, the type of routing resources used) affecting delay times between sources and loads.
delay times between sources and loads on the routed nets.
and to check for logic depth. Logic depth is reported in .twr files as logic levels (components).
datapath. This technique may be the only way to achieve high internal frequencies if the designs logic levels
are too deep.
gather information about the design.
Board Requirements into FPGA Preferences section of this document goes over an appropriate preference
file example.
constraint files.
Floorplanning).
trace hold timing checks on the clock boosted design. Refer to the Clock Boosting section of this document
for more information on clock boosting.
17-2
Lattice Semiconductor FPGA
Successful Place and Route