LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 144

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
age that is used by the DQS transition detector circuit. This voltage divider is only present on V
able on V
Lattice technical note number TN1050, LatticeECP/EC DDR Usage Guide.
Mixed Voltage Support in a Bank
The LatticeECP/EC and LatticeXP sysIO buffer is connected to three parallel ratioed input buffers. These three par-
allel buffers are connected to V
as fixed thresholds for 3.3V (V
assigned on a pin-by-pin basis, rather than tracking it with V
ratioed inputs and is independent of the bank V
have 1.2V and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresh-
olds.
Prior to device configuration, the ratioed input thresholds always track the bank V
after configuration. Output standards within a bank are always set by V
that the user can mix in the same bank.
Table 8-2. Mixed Voltage Support
V
1.2V
1.5V
1.8V
2.5V
3.3V
CCIO
REF2.
1.2V
Yes
Yes
Yes
Yes
Yes
For more information on the DQS transition detect logic and its implementation please refer to
1.5V
Yes
Input sysIO Standards
CCAUX
CCIO,
1.8V
Yes
) and 1.2V (V
V
CCAUX
2.5V
Yes
Yes
Yes
Yes
Yes
and to V
CCIO
CC
) inputs. This allows the input threshold for ratioed buffers to be
voltage. For example, if the bank V
CC
3.3V
Yes
Yes
Yes
Yes
Yes
8-4
giving support for thresholds that track with V
CCIO.
This option is available for all 1.2V, 2.5V and 3.3V
1.2V
Yes
CCIO.
1.5V
Yes
LatticeECP/EC and LatticeXP
Output sysIO Standards
Table 8-2 shows the sysIO standards
CCIO,
1.8V
CCIO
Yes
this option only takes effect
sysIO Usage Guide
is 1.8V, it is possible to
REF1
2.5V
Yes
it is not avail-
CCIO
3.3V
as well
Yes