LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 345

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

July 2004
Introduction
Lattice Semiconductor’s ispLEVER
devices, provides options to help meet design timing and logic utilization requirements. Additionally, for those
instances where objectives push the capabilities of the device architecture, ispLEVER provides the tools for meet-
ing the most challenging requirements.
For the most aggressive design requirements, the designer should become familiar with a variety of timing con-
straints (called preferences) and Place And Route (PAR) techniques for providing the optimal PAR results. This
document describes these tips and techniques. Advanced techniques in floorplanning will not be discussed in this
document. Instead they are covered in technical note number TN1010, Lattice Semiconductor Design Floorplan-
ning.
ispLEVER Place and Route Software (PAR)
In the ispLEVER design flow, after a design has undergone the necessary translation to bring it into the mapped
physical design (.ncd file) format, it is ready for placement and routing. This phase is handled by the timing-driven
PAR software program. Designers can invoke PAR from the ispLEVER Project Navigator or from the command line.
PAR performs the following:
Placement
The PAR process places the mapped physical design (.ncd file) in two stages: a constructive placement and an
optimizing placement. PAR writes the physical design after each of these stages is complete.
During constructive placement, PAR places components into sites based on factors such as:
Constructive placement continues until all components are placed. Optimizing placement is a fine-tuning of the
results of the constructive placement.
Routing
Routing is also done in two stages: iterative routing and delay reduction routing (also called cleanup). PAR writes
the physical design (.ncd file) only after iterations where the routing score has improved.
During iterative routing, the router performs an iterative procedure to converge on a solution that routes the design
to completion or minimizes the number of unrouted nets.
During cleanup routing (also called delay reduction), the router takes the results of iterative routing and reroutes
some connections to minimize the signal delays within the device. There are two types of cleanup routing that can
be performed:
www.latticesemi.com
• Takes a mapped physical design (.ncd file) and a preference file (.prf) as input files.
• Places and routes the design, attempting to meet the timing preferences in the input .prf file.
• Creates a file which can then be processed by the ispLEVER design implementation tools.
• Constraints specified in the input file (for example, certain components must be in certain locations).
• The length of connections.
• The available routing resources.
• Cost tables which assign random weighted values to each of the relevant factors. There are 100 possible
cost tables.
®
software, together with Lattice Semiconductor’s catalog of programmable
Lattice Semiconductor FPGA
Successful Place and Route
17-1
Technical Note TN1018
tn1018_02.0