LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 305

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
plete, if PROGRAMN is high, INITN will be released. If INITN is held low externally the LatticeXP will wait until it
goes high. When INITN goes high the LatticeXP begins looking for the configuration data preamble on the selected
configuration port, as determined by the CFG pins.
Once configuration is complete the internal DONE bit is set, the DONE pin goes high, and the FPGA wakes up
(enters user mode). If a CRC error is detected when reading the bitstream INITN will go low, the internal DONE bit
will not be set, the DONE pin will stay low, and the LatticeXP will not wake up.
When using SDM to program SRAM the sequence is similar but INITN is not used or monitored (INITN is driven
low). The sequence begins when the internal power-on reset (POR) is released or the PROGRAMN pin is driven
low (see Figure 13-2). The LatticeXP then tri-states the I/Os and initializes the internal SRAM and control logic.
When initialization is complete the LatticeXP begins loading configuration data from on-chip Flash.
As with non-SDM, once configuration is complete the internal DONE bit is set, the DONE pin goes high, and the
FPGA wakes up (enters user mode).
Figure 13-2. SRAM Configuration Timing Diagram
Flash Direct: Flash Direct programming is possible using the Slave Parallel port if both CFG pins are high (SDM).
Serial ports may not be used to program the Flash. Flash Direct is only valid if the DONE pin is low (the SRAM is
blank).
The sequence begins when the PROGRAMN pin is driven low. The LatticeXP tri-states the I/Os, and initializes the
internal SRAM and control logic. The LatticeXP waits for WRITEN and both CSN and CS1N pins to go low and
then looks for the programming preamble followed by the erase, program, and verify commands. Data is written
and read on the D[0:7] pins.
Once the Flash is programmed the PROGRAMN pin can be brought high to start the transfer from Flash to SRAM.
Flash Background: Flash Background programming is possible using the Slave Parallel port if both CFG pins are
high (SDM). Serial ports may not be used to program the Flash. Flash Background will not disturb the FPGA's
present configuration.
Flash Background programming may be used in both config mode and user mode (Done bit = 0 or 1). To support
Flash Background programming in user mode the PERSISTENT bit must be set to ON.
When WRITEN goes low, and CSN and CS1N are low, the FPGA will wait for the preamble and then look for the
proper commands. A low on INITN indicates an error during a Flash erase or program. Data is written and read on
the D[0:7] pins.
After programming the Flash the user may toggle the PROGRAMN pin to transfer the Flash data to SRAM.
PROGRAMN
DONE
CCLK
INITN
Initialize
13-6
Configure
LatticeXP sysCONFIG Usage Guide
Wake-Up