LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 375

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
From the Hold Report below, which was run for MIN conditions. The report shown here is for ddr_ad* only.
Find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. Then take the
min of those delays as t
===========================================================================
Preference: CLOCK_TO_OUT PORT “ddr_ad_*” 5.500000 ns CLKNET “ddr_clk_c” ;
Passed:
ddr_clk_c -)
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTREG_DEL
NCLK_DEL
ROUTE
Report:
Logical Details:
Constraint Details:
Physical Path Details:
Source:
Destination:
Data Path Delay:
Clock Path Delay:
Name
Name
Name
•
t
3.124ns delay clk to ddr_ad_4 less
1.905ns feedback compensation
0.928ns delay ddr_ad_4 to ddr_ad_4 (totaling 2.147ns) meets
0.000ns hold offset clk to ddr_ad_4 by 2.147ns
Clock path clk to ddr_ad_4:
Data path ddr_ad_4 to ddr_ad_4:
Feedback path:
CCTRL
The following path meets requirements by 2.147ns
Fanout
Fanout
Fanout
2.220ns is the maximum offset for this preference.
(min) = (3.124-1.905)
12 items scored, 0 timing errors detected.
---
---
449
---
---
136
1
--------
--------
--------
Unknown
Cell type
Port
CCTRL
Delay (ns)
0.576
0.507
0.231
1.810
3.124
Delay (ns)
0.928
0.928
Delay (ns)
0.231
1.674
1.905
0.928ns
3.124ns
(min).
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.MCLK to
(25.8% logic, 74.2% route), 2 logic levels.
(100.0% logic, 0.0% route), 1 logic levels.
LLHPPLL.NCLK to
(12.1% logic, 87.9% route), 1 logic levels.
+ 0.928
Q
Pin type
Pad
AB4.INCK to
(100.0% logic, 0.0% route), 1 logic levels.
(25.8% logic, 74.2% route), 2 logic levels.
AB4.PAD to
T26.SC to
= 2.147 ns
Site
Site
Site
18-15
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_adZ0Z_4
Cell name
ddr_ad_4
LLHPPLL.CLKIN clk_c
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
AB4.INCK clk
T26.PAD ddr_ad_4 (from ddr_clk_c)
T26.SC ddr_clk_c
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Resource
Board Timing Guidelines
(from