LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 195

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The user should specify the absolute value of the address at which the Almost Empty and Almost Full Flags will go
true. For example, if the Almost Full Flag is required to go true at the address location 500 for a FIFO of depth 512,
the user should specify the value 500 in the IPexpress.
The Empty and Almost Empty Flags are always registered with the read clock and the Full and Almost Full Flags
are always registered to the write clock.
FIFO Operation
FIFOs are not supported in the hardware. The hardware has Embedded block RAMs (EBR) which can be config-
ured in Single Port (RAM_DQ), Pseudo-Dual Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The
FIFOs in these devices are emulated FIFOs that are built around these RAMs.
Each of these FIFOs can be configured with (pipelined) and without (non-pipelined) output registers. In the pipe-
lined mode users have an extra option for these output registers to be enabled by the RdEn signal. We will discuss
the operation in the following sections.
Let us take a look at the operation of these FIFOs.
First In First Out (FIFO) Memory: The FIFO or the single clock FIFO is an emulated FIFO. The address logic and
the flag logic is implemented in the FPGA fabric around the RAM.
The ports available on the FIFO are:
• Reset
• Clock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
Let us first discuss the non-pipelined or the FIFO without output registers. Figure 9-33 shows the operation of the
FIFO when it is empty and the data starts to get written into it.
9-30