TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet
TXC-06101AILQ
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TXC-06101AILQ Summary of contents
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... Clock & Frame U.S. Patents No. 4,967,405; 5,040,170; 5,141,529; 5,265,096; 5,724,362 U.S. and/or foreign patents issued or pending Copyright 2001 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 SONET STS-1 Overhead Terminator DESCRIPTION The PHAST-1 SONET STS-1 Overhead Terminator per- forms Section, Line and Path Overhead processing for STS-1 SONET signals ...
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... Ex-Kx / TOH Ports .................................................................................................................. 145 DCC Ports .............................................................................................................................. 148 POH Ports .............................................................................................................................. 148 Ring Ports............................................................................................................................... 149 ISC Port .................................................................................................................................. 150 Rx TOH Processing................................................................................................................ 151 Rx POH Processing................................................................................................................ 156 Rx Side Alarm Hierarchy ........................................................................................................ 161 Rx Terminal Output Generation.............................................................................................. 161 Rx Terminal Outputs............................................................................................................... 164 DATA SHEET - 2 of 196 - PHAST-1 TXC-06101 PAGE TXC-06101-MB Ed. 3, April 2001 ...
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... Negative Pointer Justifications .............................................................................................. 18 14 PHAST-1 TXC-06101 Block Diagram.................................................................................... 20 15 PHAST-1 TXC-06101 Functional Pin Diagram...................................................................... 22 16 PHAST-1 TXC-06101 Actual Pin Diagram ............................................................................ 22 17 TTG and LTG 51.84 Mbit/s Input Timing ............................................................................... 39 18 TTG and LTG 6.48 Mbyte/s Input Timing .............................................................................. 40 19 TTG and LTG 19.44 Mbyte/s Input Timing ............................................................................ 41 20 Frame Phase Margin - Tx Re-Timing Disabled ...
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... ISC Port Input ...................................................................................................................... 150 77 ISC Port Output ................................................................................................................... 151 78 Loopbacks ........................................................................................................................... 178 79 Boundary Scan Schematic .................................................................................................. 185 80 PHAST-1 TXC-06101 144-Pin Low Profile Plastic Quad Flat Package .............................. 186 81 Asynchronous DS0 to/from Synchronous STS-1 Application .............................................. 187 82 Asynchronous DSX-1 Mapped to OC-1 Ring-Protected Application ................................... 187 DATA SHEET - 4 of 196 - PHAST-1 ...
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... Transport Layer Events ....................................................................................................... 182 27 Path Layer Events ............................................................................................................... 183 28 Device Layer Events............................................................................................................ 183 LIST OF EQUATIONS EQUATION 1 Reporting Hierarchy for Received Alarms ........................................................................... 160 2 Reporting Hierarchy for Transmit Alarms ............................................................................ 168 DATA SHEET LIST OF TABLES - 5 of 196 - PHAST-1 TXC-06101 PAGE PAGE TXC-06101-MB Ed. 3, April 2001 ...
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... Path Overhead (POH). The other 86 columns contain the actual payload information whose capacity is approximately 50 Mbit/s. 1. The North American Digital Hierarchy is described in ANSI standard T1.107. The ITU-T term "PDH" (Plesiochronous Digital Hierarchy) is used to refer generically to an asynchronous multiplexing structure. DATA SHEET 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... POH. The TOH contains N number of pointers: one for each of the SPEs Rows Rows DATA SHEET 90 Columns 87 Columns Payload Rows H 1 Figure 1. STS-1 Format Columns Payload Payload Figure 2. STS-N Format - 7 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... SPE is composed of VT POH and Tributary Data (Payload). The VT Pointer provides for flexible and dynamic alignment of the VT SPE within the VT, independent of other VTs in the STS-1 SPE. DATA SHEET Columns Columns Payload Rows H 1 Figure 3. STS-Nc Format VT Pointer VT POH VT VT Tributary SPE Data Figure 4. VTn Format - 8 of 196 - PHAST-1 TXC-06101 50 Mbit/s can be TXC-06101-MB Ed. 3, April 2001 ...
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... VT size. Since the PHAST-1 does not process VTs there will be no further discussion of VT characteristics 125 S VT1 125 S VT3 DATA SHEET 125 108 t = 125 S VT6 Figure 5. VT Sizes - 9 of 196 - PHAST-1 TXC-06101 VT2 107 108 TXC-06101-MB Ed. 3, April 2001 ...
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... OC-M to OC-N multiplexer where : M < N. DATA SHEET VT SPE Capacity VT1.5 VT2 VT3 VT6 107 t = 125 107 t = 250 107 t = 375 107 t = 500 S 104 140 212 428 Figure 6. VT Superframe - 10 of 196 - PHAST-1 TXC-06101 Legend Pointer Pointer Pointer Action V4 = Reserved = VT SPE Total Bytes TXC-06101-MB Ed. 3, April 2001 ...
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... DS3s PTE STE OC-M LTE DS3s PTE Section & Line DATA SHEET Path OC-M STE STE OC-N OC-N LTE Section Section Line Path Figure 7. Overhead Utilization - 11 of 196 - PHAST-1 TXC-06101 STE STE OC-N LTE DS3s PTE Section TXC-06101-MB Ed. 3, April 2001 ...
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... Figure 8. STS-1 Overhead C1/J0 C1/Z0 C1/ D11 D12 Figure 9. STS-3 Overhead - 12 of 196 - PHAST-1 TXC-06101 150 Mbit/s payload. There is Path Overhead J1 Trace B3 BIP-8 C2 Signal Label G1 Path Status F2 User H4 Multiframe Z3 Growth Z4 Growth Z5 Tandem Conn. First Column of SPE Path Overhead ( Column TXC-06101-MB Ed. 3, April 2001 ...
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... STEs, hubs, and remote NEs only defined for STS-1 number one. DATA SHEET Transport Overhead (First 9 Columns of STS-3c Frame C1/J0 C1/Z0 C1/ H1c H1c H2 H2c H2c D11 D12 Undefined Overhead Byte = 00000000 Figure 10. STS-3c Overhead - 13 of 196 - PHAST-1 TXC-06101 Path Overhead TXC-06101-MB Ed. 3, April 2001 ...
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... STS-N/Nc Line FEBE - In a signal at or above the STS-3/3c level, one byte is allocated for a Line Far End Block Error (FEBE) function. The M1 Byte is located in the third STS DATA SHEET -3 independent of the value - 14 of 196 - PHAST-1 TXC-06101 the signal or N TXC-06101-MB Ed. 3, April 2001 ...
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... A function. PDI-P is class B. G1: Path Status; Class A - One byte is allocated to convey back to the Source PTE the Sink PTE status and performance. Bits 1 through 4 are a Path FEBE. These bits are used to convey the DATA SHEET - 15 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... PTEs. However, TCM messages have priority. Since TCM ter- minating entities are not required to perform store and forward or Layer 2 termination for non- TCM messages, some or all of the preempted PTE to PTE messages may be lost and require retransmission. DATA SHEET - 16 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... H3 Byte in the frame containing the inverted I Bits. Subsequent pointers contain the new offset. DATA SHEET 90 Columns Previous SPE Start of SPE STS-1 SPE Next SPE Figure 11. STS-1 Frame H1 Byte H2 Byte LSB MSB 196 - PHAST-1 TXC-06101 125 250 S LSB TXC-06101-MB Ed. 3, April 2001 ...
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... SPE H3 J1 SPE Positive SPE Stuff Byte SPE SPE SPE SPE H3 J1 SPE SPE Negative H2 Stuff Byte (Data) J1 SPE SPE SPE - 18 of 196 - PHAST-1 TXC-06101 Frame 125 S Frame n 250 S Frame n 375 Frame 125 S Frame n 250 S Frame n 375 S TXC-06101-MB Ed. 3, April 2001 ...
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... I and D Bits are set to all "1"s. The N Bits are set to "1001" and the S Bits are set to "00". The PHAST-1 does not support concatenation but does provide a status bit indicating that a concatenation indica- tion has been received in the H1 and H2 Bytes. DATA SHEET - 19 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... TOH K1/K2 BYTES Figure 14. PHAST-1 TXC-06101 Block Diagram RECEIVE SIDE The Multiplexer at the Receive Line Input selects either the Line Side Input or the looped signal from the Trans- mit Line Output. The selected signal is applied to the Rx TOH Processor. The Rx TOH Processor Block is responsible for Framing, De-scrambling, Overhead Distribution and Overhead Processing. All Section and Line Overhead Bytes are stored in RAM and may be read through the µ ...
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... DCC Port, or the Tx Section DCC Port. Alarms are generated as a result of Rx Side anomalies, Terminal Side conditions, Alarm Port Input, Tx Ring Port Input or upon command from the µPro Interface. The Tx Line Output consists of either the Tx OH Generator Output or the looped Received Line Signal. DATA SHEET 196 - PHAST-1 TXC-06101 -K /TOH Port, the Tx Line x TXC-06101-MB Ed. 3, April 2001 ...
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... LRFR RAP/RTS ORDO OTCO STFR LTFR TAP/TTS OTDI RGCO RGFR RGDO RGDI PRCO RPS PRDO PTCO TPS PTDI Figure 15. PHAST-1 TXC-06101 Functional Pin Diagram TPDI1 110 ISCOCO TPDI0 ISCODO 112 GND TEST 114 VDD ISCOFO 116 TPCI/O TTCI/O 118 TPARI TTDI ...
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... Depending on the operating modes it may be used to define the Transmit Line start of frame. I CMOSp Datacom Reference Clock Input: 51.84/19.44/6.48 MHz clock used in Datacom Mode to generate TTCI/O or TPCI/O. This is a required input for Datacom Mode 196 - PHAST-1 TXC-06101 Name/Function DD Name/Function TXC-06101-MB Ed. 3, April 2001 ...
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... Receive Terminal Clock Output: Serial, 51.84 MHz terminal clock. Depending on the operating modes, RTCO may be derived from either RLCI or RRCI. CT8 Receive Terminal Data Output: Serial, 51.84 MHz data. Data is clocked out on the Falling Edges of RTCO 196 - PHAST-1 TXC-06101 Name/Function Name/Function Name/Function Name/Function TXC-06101-MB Ed. 3, April 2001 ...
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... Falling Edges of TPCO. When INVPCK = "1" clocked out on the Rising Edges of TPCO. CT4 Terminal Parity Output: Odd parity over TPDO(0-7), RSPE and RSYN when C1J1EN = "1" Datacom mode. When C1J1EN = "0" generated over TPDO(0-7 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... DRCI. Since it is possible for the device to power up with this pin as an output, a reset should be per- formed via pin RST to ensure correct operation. CMOS Transmit Terminal Data Input: Serial, 51.84 Mbit/s data. Data is clocked in on the Rising Edges of TTCI/ 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... TSPEI/O is clocked out on the Falling Edges of TPCI/O when INVPCK = "0" or the Rising Edges of TPCI/O when INVPCK = "1". Since it is possible for the device to power up with this pin as an output, a reset should be performed via pin RST to ensure correct operation 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... Pulse. When OA = "1" this signal occurs one clock cycle after the LSB of the K2 Byte in OTDO. When OA = "0" it occurs one clock cycle before the MSB of the A1 Byte. RAP/RTS is clocked out on the Rising Edge of ORCO 196 - PHAST-1 TXC-06101 Name/Function Name/Function TXC-06101-MB Ed. 3, April 2001 ...
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... Transmit POH Framing Pulse: Active Low transmit framing Pulse occurring one and a half clock cycles before the MSB of the J1 Byte is sampled on PTDI. TPS is clocked out on the Falling Edge of PTCO 196 - PHAST-1 TXC-06101 Name/Function Name/Function 576 kHz clock, derived 576 kHz clock, syn- TXC-06101-MB Ed. 3, April 2001 ...
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... CT4 Ring Port Data Output: Ring Port Output Data. RGDO is clocked out on the Rising Edge of RGCO. I TTLp Ring Port Data Input: Ring Port Input Data. The Ring Port data input is self clocking 196 - PHAST-1 TXC-06101 Name/Function Name/Function TXC-06101-MB Ed. 3, April 2001 ...
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... Type I TTLp µPro Interface Select: Selects the µPro Interface type as shown below: µPSEL1 µPSEL0 Low Low High High - 31 of 196 - PHAST-1 TXC-06101 Name/Function Name/Function Interface Type Low Motorola High Intel Low Undefined - DO NOT USE High Multiplexed Address/Data TXC-06101-MB Ed. 3, April 2001 ...
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... A High indicates the data transfer may take place. A Low indicates that wait states are required. Data Acknowledge Output: Motorola Interface. A Low during Read indicates that data is valid. A Low during Write indicates that data is accepted 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... TTLp Test Data Input: Serial, Boundary Scan Data Input. Information is clocked in on the Rising Edge of TCKI. I TTLp Test Mode Select Input: This signal is used to control test operations sampled on the Rising Edge of TCKI 196 - PHAST-1 TXC-06101 Name/Function Name/Function TXC-06101-MB Ed. 3, April 2001 ...
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... It must be used after power is applied and the clocks are stable. I TTLp Test Enable: An Active Low signal that invokes a TXC Test Mode. If both RST and TEST are Low all Output and Bidirectional (I/O) pins assume the tri-state condition. I ...
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... Unit Conditions 3.9 V Note 1 5.5 V Note 1 o 150 C Note ft/min linear airflow Level per EIA/JEDEC JESD22-A112 Note 2 100 % non-condensing V Note 3 Max Unit Test Conditions o 45 C/W 0 ft/min linear airflow Typ Max Unit 3.30 3.45 75 100 mA 250 345 mW TXC-06101-MB Ed. 3, April 2001 V ...
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... PHAST-1 TXC-06101 Test Conditions 3.15 V 3.45 DD 3. 3.45V (Note 1) DD Test Conditions 3.15 V 3.45 DD 3. 3.45V (Notes Test Conditions 3.15 V 3.45 DD 3. 3.45V (Note 1) DD Test Conditions 3.15 V 3.45 DD 3. 3.45V (Notes TXC-06101-MB Ed. 3, April 2001 ...
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... 3.15 -1 3.15 4.0 (Note 3. 3. 3.45V (Notes Test Conditions 3.15 V 3.45 DD 3. 3.45V (Notes 3.15 -8.0 (Note 3.15 -1 3.15 8.0 (Note 3. 3. 3.45V (Notes Test Conditions 3.15 V 3.45 DD 3. 3.45V (Notes 3.15 -8.0 (Note TXC-06101-MB Ed. 3, April 2001 ...
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... PHAST-1 TXC-06101 Test Conditions V = 3.15 -1 3.15 8.0 (Note 3. 3. 3.45V (Notes Test Conditions V = 3.15 -4.0 (Note 3.15 -1 3.15 4.0 (Note 3. 3. 3.45V (Notes Test Conditions V = 3.15 -8.0 (Note 3.15 -1 3.15 8.0 (Note 3. 3. 3.45V (Notes 1, 7) TXC-06101-MB Ed. 3, April 2001 ...
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... Figure 17. TTG and LTG 51.84 Mbit/s Input Timing DATA SHEET = 3.0 V, and Input Transitions = 1 and Input Transitions = ( CYC t t PWH PWL Symbol Min t 19.25 CYC 2 0 PWH t 45 PWL 4 196 - PHAST-1 TXC-06101 / Typ Max Unit Notes 19.29 19. 1.0 8.1 x CYC CYC CYC 4 TXC-06101-MB Ed. 3, April 2001 ...
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... RRCI/DRCI Low Time RRCI/DRCI Rise Time (10% - 90%) RRFI/DFRI Setup Time to RRCI/DRCI DATA SHEET t CYC t t PWH PWL Symbol Min Typ t 154.0 154.3 CYC 3 0.9 1 PWH PWL 7 196 - PHAST-1 TXC-06101 Max Unit Notes 154 8.1 x CYC CYC CYC 6 TXC-06101-MB Ed. 3, April 2001 ...
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... RRCI/DRCI Low Time RRCI/DRCI Rise Time (10% - 90%) RRFI/DFRI Setup Time to RRCI/DRCI DATA SHEET t CYC t PWL PWH Symbol Min t 50.0 CYC 3 0 PWH t 45 PWL 7 196 - PHAST-1 TXC-06101 Typ Max Unit Notes 51. 1.0 3.1 x CYC CYC CYC 6 TXC-06101-MB Ed. 3, April 2001 ...
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... Cross-hatched periods in waveform diagrams represent "Don’t Care" inputs or indeterminate outputs. Figure 20. Frame Phase Margin - Tx Re-Timing Disabled DATA SHEET 20 must be maintained. t Dmax Dmin C1 or C1, #3 Symbol t Dmin t Dmax - 42 of 196 - PHAST-1 TXC-06101 Unit Notes 4 TLCI Clock Periods TLCI Clock Periods TXC-06101-MB Ed. 3, April 2001 ...
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... DATA SHEET t CYC t t PWH PWL STABLE STABLE C1 MSB IF USED Symbol Min t 19.25 CYC 2 PWH t 45 PWL 4.0 SU Figure 21. Receive Line Input Timing - 43 of 196 - PHAST-1 TXC-06101 STABLE Typ Max Unit Notes 19.29 19. CYC CYC 4 TXC-06101-MB Ed. 3, April 2001 ...
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... Notes: Figure 1. See LTG Timing Characteristics ( 2. With 25 pF load DATA SHEET t CYC ( PWH PWL ( (1) (1) ( PWHO PWLO VALID VALID Symbol Min Typ t -1 PWHO PWLO 196 - PHAST-1 TXC-06101 Max Unit Notes 3 CYC CYC 1 TXC-06101-MB Ed. 3, April 2001 ...
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... Figure 23. Rx OW-APS / TOH Port Output Timing DATA SHEET t CYC PWL PWH VALID VALID Symbol Min Typ t 1732 1736 CYC 576.0 578 PWH PWL 196 - PHAST-1 TXC-06101 23 and 24. Max Unit Notes 1740 ns 581.4 5 CYC CYC 2 TXC-06101-MB Ed. 3, April 2001 ...
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... OTCO Note 1: With 25 pF Load DATA SHEET t CYC PWH PWL STABLE STABLE Symbol Min Typ 1732 1736 t CYC 576.0 578 PWH PWL 196 - PHAST-1 TXC-06101 Max Unit Notes 1740 ns 581.4 5.0 ns 5 CYC CYC 2 TXC-06101-MB Ed. 3, April 2001 ...
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... R t CYC PWL PWH VALID Symbol Min Typ t 1732 1736 CYC t -5.0 0 PWH PWL 196 - PHAST-1 TXC-06101 25 and 26. Figures 27 and 28 Max Unit Notes 5.22 µs 5 CYC CYC 2 Max Unit Notes 1740 ns 5 CYC CYC 2 TXC-06101-MB Ed. 3, April 2001 ...
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... Symbol Min Typ t 5.20 5.21 CYC 0 PWH PWL 7 CYC PWH PWL STABLE Symbol Min Typ t 1732 1736 CYC 0 PWH PWL 7 196 - PHAST-1 TXC-06101 Max Unit Notes 5.22 µs 2 CYC CYC 2 Max Unit Notes 1740 ns 2 CYC CYC 2 TXC-06101-MB Ed. 3, April 2001 ...
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... Z5, LSB VALID VALID Symbol Min t CYC t -5 761 PWH t 761 PWL t R Figure 29. Rx POH Port Output Timing - 49 of 196 - PHAST-1 TXC-06101 30 depicts the input timing. Typ Max Unit Notes 1697 ns 0 5 926 ns 771 ns 2 TXC-06101-MB Ed. 3, April 2001 ...
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... Note 1: With 25 pF Load DATA SHEET Figure 30. Tx POH Port Input Timing t CYC PWH PWL STABLE Z5, LSB Symbol Min t CYC 761 PWH t 761 PWL 7 196 - PHAST-1 TXC-06101 STABLE J1, MSB Typ Max Unit Notes 1697 ns 5 926 ns 771 ns 2 TXC-06101-MB Ed. 3, April 2001 ...
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... R t 1506 UI Figure 32. Tx Ring Port Input Timing - 51 of 196 - PHAST-1 TXC-06101 32 depicts the input timing PRDIH VALID Typ Max Unit Notes 1543 1550 ns 5.0 ns 2.5 ns 771 ns 771 ns 2.0 ns Typ Max Unit Notes 6.0 ns 6.0 ns 1543 1580 ns TXC-06101-MB Ed. 3, April 2001 ...
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... DATA SHEET t t PWH PWL (1) ( (1) ( LSB MSB (V1) Symbol Min Typ t RTCO -1 PWHO PWLO 196 - PHAST-1 TXC-06101 36 depicts the outputs when the t t PWHO PWLO t FO LSB Max Unit Notes 3 CYC CYC TXC-06101-MB Ed. 3, April 2001 ...
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... DATA SHEET Figure 34. SPE-Only Output Timing t t PWH PWL (1) ( (1) ( LSB MSB J1/(V1) Symbol Min t RTCO -1 6 PWHO t 40 PWLO 196 - PHAST-1 TXC-06101 t t PWHO PWLO t FO LSB Typ Max Unit Notes 0 3 CYC CYC TXC-06101-MB Ed. 3, April 2001 ...
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... CYCO t PWLO VALID (V1) VALID Symbol Min Typ 8 t CYCO 1 t TPCO -5.0 0 -5 PWHO PWLO 196 - PHAST-1 TXC-06101 (1) (1) PWH ( (1) t PWHO t FO Max Unit Notes CYC CYC 2,6 24 3,6 2 CYCO CYCO TXC-06101-MB Ed. 3, April 2001 ...
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... HZ HI-Z A1, #1 VALID HI-Z HI-Z C1/J1/(V1) HI-Z VALID VALID # Symbo Min PWHO t 40 PWLO - 55 of 196 - PHAST-1 TXC-06101 t PWH ( HI-Z HI-Z HI-Z HI Typ Max Unit Notes 3 5 0 CYC CYC TXC-06101-MB Ed. 3, April 2001 ...
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... TTDI, TSPEI/O, or TSYNI/O Setup Time to TTCI/O DATA SHEET t CYC t t PWH PWL STABLE STABLE STABLE Symbol Min Typ t 19.25 19.29 CYC 2 PWH PWL 4 196 - PHAST-1 TXC-06101 42 depicts the inputs when the Max Unit Notes 19. CYC CYC 4 TXC-06101-MB Ed. 3, April 2001 ...
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... Figure 1. See LTG Timing Characteristics ( 2. With 25 pF Load. DATA SHEET t CYC ( PWH PWL ( PWHO PWLO STABLE STABLE t D Symbol Min t TTCI PWHO t 40 PWLO 17 196 - PHAST-1 TXC-06101 t H Typ Max Unit Notes 3 CYC CYC 1 TXC-06101-MB Ed. 3, April 2001 ...
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... Note 1: Sampling occurs on Falling Edge of TPCI/O (dotted line) when INVPCK = "1". DATA SHEET t CYC t t PWH PWL STABLE STABLE Symbol Min Typ t 154.0 154.3 CYC 3 PWH PWL 7 196 - PHAST-1 TXC-06101 Max Unit Notes 154 CYC CYC 6 TXC-06101-MB Ed. 3, April 2001 ...
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... PWH PWL PWH PWL (1) (1) (1) ( (1) (1) (1) t CYCO t t PWHO PWLO ( Symbol Min t CYCO t -5 0 PWHO t 40 PWLO and 18 196 - PHAST-1 TXC-06101 (1) ( STABLE STABLE Typ Max Unit Notes CYC 1 3 0 CYCO CYCO 2 TXC-06101-MB Ed. 3, April 2001 ...
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... Sampling occurs on Falling Edge of TPCI/O (dotted line) when INVPCK = "1". 2. With 25 pF Load DATA SHEET t CYC t t PWH PWL ( STABLE STABLE STABLE STABLE Symbol Min Typ t 50 51.44 CYC 3 PWH PWL 7 196 - PHAST-1 TXC-06101 STABLE STABLE Max Unit Notes ns 6 CYC CYC 6 TXC-06101-MB Ed. 3, April 2001 ...
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... TSYNI/O is High during all three slots of C1 time. DATA SHEET t t PWL PWH (1) (1) t CYC ( ( PWLO PWHO ( STABLE STABLE ( Symbol Min Typ PWHO t 40 PWLO 19 196 - PHAST-1 TXC-06101 t RO STABLE #1 #2 Max Unit Notes 0 CYC CYC 2 TXC-06101-MB Ed. 3, April 2001 ...
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... With 25 pF Load DATA SHEET Figure 43. ISC Port Output Timing t CYC E2, LSB C1 VALID VALID Symbol Min t CYC t ISCOCO -5 145 PWH t 145 PWL 196 - PHAST-1 TXC-06101 44 depicts the input timing Typ Max Unit Notes 579 ns 1 5 TXC-06101-MB Ed. 3, April 2001 ...
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... With 25 pF Load. DATA SHEET Figure 44. ISC Port Input Timing t CYC PWH PWL STABLE E2, LSB Symbol Min Typ t 579 CYC 145 PWH t 145 PWL 196 - PHAST-1 TXC-06101 t R STABLE C1, MSB Max Unit Notes ns 1 5 TXC-06101-MB Ed. 3, April 2001 ...
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... PWL1 DATA SU2 PWL2 Symbol Min t RDY 0 2 ALE PWH t 40 PWL1 t 0.0 PWL2 t ALE 7.0 SU1 t 0.0 SU2 RDY 325 196 - PHAST-1 TXC-06101 ADDRESS ADDRESS VALID HI Typ Max Unit Notes 9 7 1220 TXC-06101-MB Ed. 3, April 2001 ...
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... Two-byte read/write is a read or write of the low byte of a 16-bit counter when CNT16EN = "1". DATA SHEET RD of next read of a different address max of: RDY of last two-byte read* to same address last one-byte write to same address last two-byte write* to same address 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... H2 t SU2 DATA t SU3 PWL 2 Symbol Min t 2 ALE PWH t 20 PWL1 t 0.0 PWL2 t ALE 7.0 SU1 t 10 SU2 t 0.0 SU3 900 196 - PHAST-1 TXC-06101 HI-Z ADDRESS VALID HI Typ Max Unit Notes 9 900 TXC-06101-MB Ed. 3, April 2001 ...
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... Two-byte read/write is a read or write of the low byte of a 16-bit counter when CNT16EN = "1". DATA SHEET RD of next read of a different address RD of next read of a different address WR or RD. RDY of last two-byte read* to same address last two-byte write* to any address last one-byte write to any address 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... Min PWL1 t 10 PWH1 t 325 W1 t 0.0 PWL2 RD t 0.0 SU1 t 0.0 SU2 RD of next read of a different address max of 196 - PHAST-1 TXC-06101 HI PWH1 t D4 HI-Z Typ Max Unit Notes 9 1220 TXC-06101-MB Ed. 3, April 2001 ...
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... RD of next read of a different address RD of next read of a different address WR or RD. RDY of last two-byte read* to same address last two-byte write* to any address last one-byte write to any address 196 - PHAST-1 TXC-06101 HI-Z Typ Max Unit Notes 9 900 TXC-06101-MB Ed. 3, April 2001 ...
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... SEL of next read of a different address SEL max of: DTK of last two-byte read* to same address), or SEL of last one-byte write to same address), or SEL of last two-byte write* to same address 196 - PHAST-1 TXC-06101 I I-Z Typ Max Unit Notes 9 1220 TXC-06101-MB Ed. 3, April 2001 ...
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... SEL of next read of a different address SEL of next read of a different address SEL. DTK of last two-byte read* to same address), or SEL of last two-byte write* to any address), or SEL of last one-byte write to any address 196 - PHAST-1 TXC-06101 HI-Z Typ Max Unit Notes 900 TXC-06101-MB Ed. 3, April 2001 2 ...
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... TDI Hold Time after TCKI TDO Delay after TCKI DATA SHEET Figure 51. Boundary Scan Timing t H(1) t SU( Symbol Min t 50 PWH t 50 PWL t 3.0 SU(1) t 2.0 H(1) t 3.0 SU(2) t 2.0 H( 196 - PHAST-1 TXC-06101 Max Unit 7.0 ns TXC-06101-MB Ed. 3, April 2001 ...
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... MSB DATA SHEET Figure 52. Overall Memory Map Order of Transmission - 73 of 196 - PHAST-1 TXC-06101 USAGE Status, Control, Hi Byte Tx POH not equipped Tx TOH Status & Control Rx POH Rx TOH PHAST-1 0 bit position LSB Transmission TH 8 Convention TXC-06101-MB Ed. 3, April 2001 ...
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... Rx Line E2: Line Order Wire Byte - This byte is also available at the Rx OA/TOH Port Line Z1: 1 Growth Byte - This byte is debounced and stored in Loca- tion 05A[H]. This Byte is also optionally available at the Rx OA/TOH Port 196 - PHAST-1 TXC-06101 Description Description TXC-06101-MB Ed. 3, April 2001 ...
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... WARNING: This is for test purposes only. The Payload does not track the pointer value written in these locations. Rx Insert H3: Rx Terminal Port Data H3 Byte value when Rx Re-timing is enabled and a Pointer Decrement is not performed 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
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... Input ISC Port if ISC Port Option is enabled. Rx Insert K1 and K2: 1. bytes, written by µPro multiplexed into Rx Terminal Port Data if insertion option is enabled 2. bytes received at Input ISC Port if ISC Port Option is enabled - 76 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 77
... Rx B2 Error Mask: the contents of this location are exclusive-OR gated, bit by bit, with the B2 Byte output at the Rx Terminal Port. Frm-2 (Z1, Z2, C1, F1, K1, K2): respective bytes received two frames ear- lier where ; 052[H] = Frm-2 Z1 and 057[H] = Frm-2 K2. Internal Use - Do Not Access - 77 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 78
... B3CCV/B3SCV: Bits 0-3 are the B3CCV Parameter. Bits 4-7 are the B3SCV Parameter. See Table 15 for B3EBER Parameter settings. B3 Set: see Table 15 for B3EBER Parameter settings. B3 Clear: see Table 15 for B3EBER Parameter settings. Internal Use - Do Not Access - 78 of 196 - PHAST-1 TXC-06101 F+4 F TXC-06101-MB Ed. 3, April 2001 ...
Page 79
... Rx Insert C2: byte to be multiplexed into Rx Terminal Port Data if inser- tion option is enabled Rx Insert G1: byte to be multiplexed into Rx Terminal Port Data if inser- tion option is enabled Rx Insert F2: byte to be multiplexed into Rx Terminal Port Data if inser- tion option is enabled - 79 of 196 - PHAST-1 TXC-06101 TH Growth Bytes - These bytes TXC-06101-MB Ed. 3, April 2001 ...
Page 80
... Internal Use - Do Not Access Frm-2 F2: F2 Byte received two frames earlier C2 Expect: value with which Rx Line C2 Location is compared for Signal Label Mismatch Frm-2 (Z3, Z4 and Z5): respective bytes received two frames earlier where : 0E5[H] = Frm-2 Z3 and 0E7[H] = Frm 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 81
... Bit 1 Bit 0 C2MIS C2UNEQ RLOM Unused RLOF RSEF RLOS RAPS RBUSCOL HWRST RPJOF LPJOF REG4 REG5 REG78 RRAPS RRPTR TRLOOP LTE RRFRM RRB1 TIEN PIEN -VE CNT16EN RSWRES TTOHEN C2MPAIS C2UPAIS RLEAIS MBSEL1 MBSEL0 INVINT S1 S0 C1J1EN OA B3MULT0 TXC-06101-MB Ed. 3, April 2001 ...
Page 82
... Tx Line Port Data if insertion option is enabled. 128[ and 130[H] = D12. These locations may be written by the µPro, or contain informa- OA tion input at the Tx Section DCC Port or optionally at the Tx OA/TOH Port. Reserved: Reserved for future use - 82 of 196 - PHAST-1 TXC-06101 Description TXC-06101-MB Ed. 3, April 2001 ...
Page 83
... Read. Counting is inhibited upon declaration of TLOC, TLOS, TLOF, or TAIS- C1J1EN Error Count: count of B1 Errors that are incoming at the Tx Ter- minal Port. This is an 8-Bit, Clear on Read, Roll Over Counter. Counting is inhibited upon declaration of TLOC, TLOS, or TLOF, or INHTB1C 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 84
... Terminal Port where : 1C1[ and 1C7[ Internal Use - Do Not Access Tx Insert C2: Signal Label Byte - information to be multiplexed into Tx Line Port Data if insertion option is enabled. This location may be written by the µPro or contain information input at the Tx POH Port 196 - PHAST-1 TXC-06101 Description Description TXC-06101-MB Ed. 3, April 2001 ...
Page 85
... Tx B3 Error Count: count of B3 Errors that are incoming at the Tx Ter- minal Port. This is an 8-Bit, Clear on Read, Roll Over Counter. Counting is inhibited upon declaration of TLOC, TLOS, TLOF, TAIS-L, TAIS-P or TLOP or if TPATH = "1". NOT EQUIPPED - 85 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 86
... C2UPRDI ENFSTUA ENLSTUA STLRDI B2ELRDI DRCOFA LOTR TFIFOE TLOF TSEF TLOS LORG RGRDI-P RGRDI-L RLAISC TPAISC TLAISC TRAPS EXAPS RTLOOP PTE RXRTM RRB2 DETSEL INC DEC RA2E TE2A TA2E DFRIEN TDDLY TZ3EXT TZ4EXT TZ5EXT TXZ1EXT TXZ2EXT TXE2EXT TXC-06101-MB Ed. 3, April 2001 ...
Page 87
... RLOC, RLOS, RLOF or RAIS-L is declared inhibited if RLOC, RLOS or RLOF is declared or if DISRLAL = "1" inhibited if RLOC, RLOS, RLOF or RAIS-L is declared inhibited if RLOC or RLOS is declared inhibited if RLOC or RLOS is declared inhibited if RLOC is declared If TRLOOP = "1" Looped Data is monitored See Note 2. TXC-06101-MB Ed. 3, April 2001 ...
Page 88
... RAIS-L, RLOP or RAIS-P is declared 0F5, see Note 2. note 1 inhibited if RLOC, RLOS, RLOF, RAIS-L, RLOP or RAIS-P is declared inhibited if RLOC, RLOS, or RLOF is declared or if DISRLAL = "1" inhibited if RLOC, RLOS, or RLOF is declared or if DISRLAL = "1" 0F5, see Note 2. 0F5, see Note 2. TXC-06101-MB Ed. 3, April 2001 ...
Page 89
... TLOS, TLOF or TAIS-L is declared or if C1J1EN = "1" inhibited if TLOC, TLOS or TLOF is declared or if DISTLAIS = "1" inhibited if TLOC, TLOS, TLOF or TAIS-L is declared or if C1J1EN = "1" inhibited if TLOC or TLOS is declared or if C1J1EN = "1" inhibited if TLOC or TLOS is declared or if C1J1EN = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 90
... B2 Error Rate less than 196 - PHAST-1 TXC-06101 Comments inhibited if TLOC is declared inhibited if DISTBPE = "1" Comments inhibited if RLOC or RLOS is declared or TRLOOP = "1" or STS1 = "1" inhibited if RLOC or RLOS is declared 3 inhibited if RLOC, RLOS, RLOF or RAIS-L is declared or if DISRLAL = "1" See note 4. TXC-06101-MB Ed. 3, April 2001 ...
Page 91
... RLOS, RLOF or RAIS-L is declared inhibited if RLOC, RLOS, RLOF, RAIS-L, RAIS-P or RLOP is declared See notes 1, 2 and 3. inhibited if RLOC, RLOS, RLOF, RAIS-L, RAIS-P or RLOP is declared See notes 1 and 2. inhibited if RLOC, RLOS, RLOF, RAIS-L, RAIS-P or RLOP is declared or H4INT = "0" TXC-06101-MB Ed. 3, April 2001 ...
Page 92
... RCLK = "0" inhibited if SPE = "0", RCLK = "0" and RXRTM = "1" 1F5, see Note 2. inhibited if RLOC, RLOS or RLOF is declared or RE2A = "0" inhibited if LOTR = "1" inhibited if LOTR = "1", LORG = "1" or RING = "0". inhibited if LOTR = "1", LORG = "1" or RING = "0". TXC-06101-MB Ed. 3, April 2001 ...
Page 93
... TLOC, TLOS, TLOF or TAIS-L is declared or if C1J1EN = "1" inhibited if TLOC, TLOS or TLOF is declared or TE2A = "0" 1EC, see Note 3. Valid only in Datacom Mode. 1EC, see Note 3. inhibited when: SPE-only 0 0 Datacom 0 1 C1J1EN 0 - TXRTM 0 0 1EC, see Note 4. TXC-06101-MB Ed. 3, April 2001 ...
Page 94
... RLOS, RLOF, RAIS-L, RLOP or RAIS-P is declared Inhibited if RLOC, RLOS, RLOF, RAIS-L, RLOP or RAIS-P is declared Inhibited if RLOC, RLOS, RLOF, RAIS-L, RLOP or RAIS-P is declared Inhibited if RLOC, RLOS, RLOF, RAIS-L, RLOP or RAIS-P is declared See note 1. "01" or inhibited if RLOC, RLOS or RLOF is declared TXC-06101-MB Ed. 3, April 2001 ...
Page 95
... Read of Rx FEBE-P Counter µPro Read of Rx FEBE-L Counter µPro Read of the counter which has overflowed µPro Read of the Rx Pointer Jus- tification Counter µPro Read of the Local Pointer Justification Counter - 95 of 196 - PHAST-1 TXC-06101 Comments Exit TXC-06101-MB Ed. 3, April 2001 ...
Page 96
... No Tx Terminal conditions exist that would cause an AIS Alarm to be output on the Tx Line if the functions were enabled 196 - PHAST-1 TXC-06101 Comments See RRAIS and RA2E. See RRAIS and RA2E. See TRAIS and TA2E. See TRAIS and TA2E. TXC-06101-MB Ed. 3, April 2001 ...
Page 97
... All latched Bits = "0" in Status Register 5 All bits in Status Register 7 and all of Bits 7-4 in Status Register 8 = "0" 196 - PHAST-1 TXC-06101 Comments 0F0[H] 0F1[H] 0F2[H] 0F3[H] 0E8[H] 0E9[H] 0EA[H] 0EB[H] 1F0[H] 1F1[H] 1F2[H] 1F3[H] 1E8[H] 1E9[H] 0F6[H] 1F6[H], Bits 7-4 TXC-06101-MB Ed. 3, April 2001 ...
Page 98
... TOH Insert RAM Location normal operation - 98 of 196 - PHAST-1 TXC-06101 Comments Notes 1, 2 Notes 1, 2 Notes Notes 1, 2 Note 4 See H4INT. Notes 1, 2 This is for test purposes only. Payload does not track insert location H1 and H2 values. See LPAISEN and LPAISSEL. TXC-06101-MB Ed. 3, April 2001 ...
Page 99
... C1 Byte from the Rx Line or ISC Port. outgoing Terminal Data contains Z1 Byte from the Rx Line or ISC Port. outgoing Terminal Data contains Z2 Byte from the Rx Line or ISC Port 196 - PHAST-1 TXC-06101 Comments Notes 1, 2 Notes 1, 2 Notes 1, 2 Notes 1, 2 TXC-06101-MB Ed. 3, April 2001 ...
Page 100
... Rx Terminal = Terminal AIS-P Insertion & =1 & =1 & =1 & =1 & =1 & & & & & 100 of 196 - PHAST-1 TXC-06101 Comments LEGEND & = Logical AND + = Logical Control State LEGEND & = Logical AND + = Logical Control State Insert AIS Terminal TXC-06101-MB Ed. 3, April 2001 ...
Page 101
... Tx Terminal Port is Serial. Rx Ter- minal Port has both Serial and Par- allel Interfaces active. disables INT/IRQ Pin - 101 of 196 - PHAST-1 TXC-06101 Comments Section Termi- nating Equip- ment Mode if LTE = "0" and PTE = "0" Notes 1, 2 Notes Comments Notes See Table 1. TXC-06101-MB Ed. 3, April 2001 ...
Page 102
... Path Layer Interrupts interrupts only on positive edges of alarms - 102 of 196 - PHAST-1 TXC-06101 Comments LEGEND & = Logical AND + = Logical Logical NOT = = Control State & Tx Line + & K2 Byte Bits & & effective only "1" See Table 26. See Table 27. TXC-06101-MB Ed. 3, April 2001 ...
Page 103
... Rx Line Level Alarms and B1, B2, FEBE-L Counters enabled. Rx Side B1, B2, B3, FEBE-L and FEBE-P Counters are 8 bits. terminates Rx Side Reset. Normal operation resumed. µPro has Write and Read access to Rx TOH Insert RAM Locations. - 103 of 196 - PHAST-1 TXC-06101 Comments Note 1 Note 1 TXC-06101-MB Ed. 3, April 2001 ...
Page 104
... Rx Terminal Port RLE1 condition excluded from equation for AIS-P and AIS-L inser- tion at Rx Terminal Port - 104 of 196 - PHAST-1 TXC-06101 Comments See RRAIS See RRAIS See RRAIS See RRAIS See RRAIS See RRAIS See RRAIS See RRAIS TXC-06101-MB Ed. 3, April 2001 ...
Page 105
... Low, Low (Motorola). - 105 of 196 - PHAST-1 TXC-06101 Comments See Table 28 Notes 1, 2 Effective only in Datacom Mode Note 3 Effective only in Datacom Mode Note 3 Note 1 only enabled if Pin MBEI is Low see ENFSTUA and ENLSTUA see TMBSEL0 and TMBSEL1 TXC-06101-MB Ed. 3, April 2001 ...
Page 106
... A1/A2 and H1/H2 are used for Frame and SPE alignment at Tx Terminal Port. all TOH Bytes output and input at Rx and Tx OA/TOH Ports, respec- tively - 106 of 196 - PHAST-1 TXC-06101 Comments Note 4 Note 1 See RPATH, TXH4INS, TPATH Note 1 Note 2 Note 3 TXC-06101-MB Ed. 3, April 2001 ...
Page 107
... Bits 1-4 of the G1 Byte in the Tx Line Port Data are not overwritten. Tx Line FEBE-P Insertion =1 & & & / & 107 of 196 - PHAST-1 TXC-06101 Comments Notes 1, 2 Notes LEGEND & = Logical AND + = Logical Logical NOT = = Control State Tx Line G1 Byte Bits TXC-06101-MB Ed. 3, April 2001 ...
Page 108
... RDI-PPD inser- tion at Tx Line Port. - 108 of 196 - PHAST-1 TXC-06101 Comments See note 5. LEGEND & = Logical AND + = Logical Logical NOT = = Control State & & & Tx Line & Byte & RDI-P Bits & & & Tx Line + G1 Byte RDI-P Bits TXC-06101-MB Ed. 3, April 2001 ...
Page 109
... RDI- PCD insertion at Tx Line Port. Rx Terminal Outputs are tri-stated during the first unassigned slot in 19.44 Mbyte/s mode. Rx Terminal Outputs are tri-stated during the last unassigned slot in 19.44 Mbyte/s mode. - 109 of 196 - PHAST-1 TXC-06101 Comments Note 4 Note 4 TXC-06101-MB Ed. 3, April 2001 ...
Page 110
... Port. Tx TOH RAM Insert K1 and K2 Byte Locations written by µPro. normal operation - 110 of 196 - PHAST-1 TXC-06101 Comments Note 1 See TXSDEXT Note 1 See TXLDEXT Notes 1, 2 See TXE1EXT Note 1 See TXE2EXT Notes 3, 4 See J1SYNCEN Note 1 See EXAPS Note 5 TXC-06101-MB Ed. 3, April 2001 ...
Page 111
... Insert + & AIS Line = 111 of 196 - PHAST-1 TXC-06101 Comments Note 1 See TXF1EXT Note 1 See TXC1EXT J0EN(0,1) Note 1 See TXZ1EXT Note 1 See TXZ2EXT LEGEND & = Logical AND + = Logical Control State LEGEND & = Logical AND + = Logical Control State TXC-06101-MB Ed. 3, April 2001 ...
Page 112
... Equipment Mode for AIS transmis- sion and Introduction. Rx Re-timing enabled. outgoing Terminal Data contains B2 Byte from the Rx Line or the ISC Port. - 112 of 196 - PHAST-1 TXC-06101 Comments Section Termi- nating Equip- ment Mode if LTE = "0" and PTE = "0" note 2 notes 3, 4 TXC-06101-MB Ed. 3, April 2001 ...
Page 113
... Tx Re-timing disabled DRCI is 6.48 MHz and Datacom Reference Frame Input is DFRI - 113 of 196 - PHAST-1 TXC-06101 Comments notes 1, 2 notes notes notes notes notes See RETSEL Table 2 note 10 MHz and Datacom effective only if Pin MBEI is High and PARA = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 114
... PHAST-1 TXC-06101 Comments These bits must be used with extreme cau- tion. Consecu- tive PJs will cause down- stream alarms. Multiple PJs can cause FIFO spills. MHz Clock then TLCI and TFRI must MHz Reference TXC-06101-MB Ed. 3, April 2001 ...
Page 115
... Comments See TFRMEXT See TRAIS Rx Ring Port Information is always gener- ated and output See TRLRDI, TPRDIEN, TLFEBEEN and LEGEND TPFEBEEN. & = Logical AND + = Logical Control State LEGEND & = Logical AND + = Logical Logical NOT = = Control State See RLE1 TXC-06101-MB Ed. 3, April 2001 ...
Page 116
... E1 = & + "All 1" & "All 0" & & E1 Byte incoming at Tx Terminal Port not interpreted as AIS Indica- tion. - 116 of 196 - PHAST-1 TXC-06101 Comments LEGEND & = Logical AND + = Logical Logical NOT = = Control State + Rx Term. E1 Byte TXC-06101-MB Ed. 3, April 2001 ...
Page 117
... E1 Byte outgoing at Tx Line Port not used for AIS Indication. Tx Line E1 Alarm Insertion & & & + "All 1" "All 0" & 117 of 196 - PHAST-1 TXC-06101 Comments LEGEND & = Logical AND + = Logical Logical NOT = = Control State & Line & E1 Byte & TXC-06101-MB Ed. 3, April 2001 ...
Page 118
... TSPEI/O to sampling of data at Tx Terminal Port is: Serial Datacom - 1½ bit times to MSB of serial data (See Figure 62) Parallel Datacom - 2 clock times (See Figures 64 and 66) - 118 of 196 - PHAST-1 TXC-06101 Comments Note 1 Note 1 Note 2 effective only if LPAISEN = "1" effective only in Datacom Mode 64 and 66) TXC-06101-MB Ed. 3, April 2001 ...
Page 119
... Tx POH Insert RAM Z3 Location will be written by µPro. - 119 of 196 - PHAST-1 TXC-06101 Comments See TPATH, J1SYNCEN and J0RWEN. See TPATH. See TPATH. See TPATH. LEGEND & = Logical AND + = Logical Logical NOT = = Control State Tx Line H4 Byte Bits 7, 8 See TPATH. TXC-06101-MB Ed. 3, April 2001 ...
Page 120
... Tx POH Insert RAM Location. DATA SHEET Conditions Bit Equal to "1" Bit Equal to "0" Tx POH Insert RAM Z4 Location will be written by µPro. Tx POH Insert RAM Z5 Location will be written by µPro. - 120 of 196 - PHAST-1 TXC-06101 Comments See TPATH. See TPATH. TXC-06101-MB Ed. 3, April 2001 ...
Page 121
... TFRM-EXT Tx Framing Bytes External Con- trol: Insert Tx TOH RAM Locations contain A1 and A2 Bytes from Tx TOH port. 6 TXC1-EXT Tx C1/J0 Byte External Control: Insert Tx TOH RAM Location(s) contains C1 Byte(s) from Tx TOH Port. 5 TXE1-EXT Tx E1 Byte External Control: Insert Tx TOH RAM Location con- tains E1 Byte from Tx TOH Port ...
Page 122
... Data not forced. Excess B2 Error condition excluded from equation for RDI-L insertion at Tx Line Port. - 122 of 196 - PHAST-1 TXC-06101 Comments See TRLD and LDCCEN. LEGEND & = Logical AND + = Logical Logical NOT = = Control State See TRLRDI. Note 1 See TRLRDI. TXC-06101-MB Ed. 3, April 2001 ...
Page 123
... See RCLK, Table 2. B2 Excess BER calculation must be disabled when Parame- Scale Factor ters or the Multiplier are 1 10 changed disabled disabled B3 Excess BER calculation must be disabled when Parame- Scale Factor ters or the Multiplier are 1 10 changed disabled disabled TXC-06101-MB Ed. 3, April 2001 ...
Page 124
... External D4-D12 Bytes are accepted from the Tx TOH Port. 5 STLAIS Send Tx Line AIS: AIS-L inserted in Tx Line Port Data 4 TEST1 TXC Test Mode 1: test active 3 TEST2 TXC Test Mode 2: test active 2 LINLOOP Line Loop Back: Rx Line input looped back to Tx Line output ...
Page 125
... Terminates chip reset. Normal operation is resumed - 125 of 196 - PHAST-1 TXC-06101 Comments effective only if J0EN(1,0) = "01" See TRLRDI. effective only if J0EN(1,0) = "01" Notes 1, 2 See J0RWEN, TRC1 and TXC1EXT. effective only if Pin MBEI is Low See MBSEL0 and MBSEL1 TXC-06101-MB Ed. 3, April 2001 ...
Page 126
... Excess B3 Error condition excluded from equation for RDI- PCD insertion at Tx Line Port TOH conditions excluded from equation for RDI-PSD insertion at Tx Line Port "110" or "111". - 126 of 196 - PHAST-1 TXC-06101 Comments Note 1 Notes 1, 2 Notes 1, 2 Note 3 Note 3 TXC-06101-MB Ed. 3, April 2001 ...
Page 127
... Bit 6) The interaction of these controls is hierarchical in nature as shown in Table 1. DATA SHEET 256 [H], Bit z) and Control Register number n (0-19) = Status Register number n (0- the Register’s Address in Hex = the Bit Number (0-7) - 127 of 196 - PHAST-1 TXC-06101 0 y [H] TXC-06101-MB Ed. 3, April 2001 ...
Page 128
... Mbyte/s parallel outputs are active. DATA SHEET DATACOM PARA 0 - Parallel SONET - 19.44 Mbyte Parallel Datacom - 19.44 Mbyte Serial SONET 0 1 Parallel SONET - 6. 48 Mbyte Serial Datacom 1 1 Parallel Datacom - 6. 48 Mbyte SPE-only Table 1. Primary Operating Modes - 128 of 196 - PHAST-1 TXC-06101 P.O.M. TXC-06101-MB Ed. 3, April 2001 ...
Page 129
... Mbyte/s Parallel 51.84 DFRI 6.48 Mbyte/s Parallel - 129 of 196 - PHAST-1 TXC-06101 Rx Terminal Output RRFI 19.44 Mbyte/s Parallel RXFR 1. Serial 2. 6.48 Mbyte/s Par- allel RRFI 6.48 Mbyte/s Parallel RRFI 1. Serial 2. 6.48 Mbyte/s Par- allel Tx Terminal Port Mode TXC-06101-MB Ed. 3, April 2001 ...
Page 130
... Terminal Timing 1 - External Tx Timing - - External Tx Timing Table 4. Tx Timing Selection - 130 of 196 - PHAST-1 TXC-06101 Clock Input Frame Input TLCI TFRI TLCI TFRI DRCI DFRI TLCI TFRI DRCI DFRI TLCI TFRI TTCI/O TSYNI/O or A1/A2 TLCI TFRI TLCI TFRI TXC-06101-MB Ed. 3, April 2001 ...
Page 131
... RFREN (CR3; 0FB[H], Bit 6). The FIFO may also be re-centered with RRFIFO (CR3; 0FB[H], Bit 5). DATA SHEET RCLK RXRTM - - Enabled - - Enabled 0 0 Enabled 0 1 Disabled 1 - Enabled Table 5. Rx Re-Timing Control - 131 of 196 - PHAST-1 TXC-06101 Rx Re-Timing TXC-06101-MB Ed. 3, April 2001 ...
Page 132
... These features must be used judiciously. If either is enabled, disabling must occur within two Frames to prevent multiple PJs. In addition, consecutive, forced PJs may cause FIFO spills. DATA SHEET C1J1EN TXRTM - - Enabled - 0 Disabled - 1 Enabled - - Enabled 0 0 Disabled 0 1 Enabled 1 - Enabled - - Enabled Table 6. Tx Re-Timing Control - 132 of 196 - PHAST-1 TXC-06101 1 . FIFO Tx Re-Timing TXC-06101-MB Ed. 3, April 2001 ...
Page 133
... DFRI is sampled by DRCI Datacom Mode, PARA = "1" 1. TDDLY = "0" bit times after DFRI is sampled by DRCI 2. TDDLY = "1" bit times after DFRI is sampled by DRCI TDDLY is (CR12; 1FC[H], Bit 0). DATA SHEET - 133 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 134
... SPE lsb msb lsb msb Figure 53. Tx Line Format - 134 of 196 - PHAST-1 TXC-06101 IF J1 TIME 6½ 7½ C1/J0 SPE lsb msb lsb 3½ SPE A1 A2 lsb msb lsb msb FRAME N-1 FRAME N TXC-06101-MB Ed. 3, April 2001 ...
Page 135
... DATA SHEET C1 lsb msb LSB. TTDI, TSPEI/O and TSYNI/O are clocked in on the C1 lsb msb C1 TIME - 135 of 196 - PHAST-1 TXC-06101 LSB. RSPE is J1 Vx,1 lsb msb lsb J1 Time V1 Time (IF ENABLED) J1 Vx,1 lsb msb lsb J1 Time V1 Time (IF PRESENT) TXC-06101-MB Ed. 3, April 2001 ...
Page 136
... INVPCK = "0" TPDI TSPEI/O (input) TSYNI/O (input) TPARI Figure 57. Tx Terminal Port Parallel 6.48 Mbyte/s SONET Format DATA SHEET PARALLEL RRCI PERIODS C1 C1 TIME C1 C1 TIME - 136 of 196 - PHAST-1 TXC-06101 J1 Vx,1 J1 Time V1 Time (IF ENABLED) J1 Vx,1 J1 Time V1 Time (IF PRESENT) TXC-06101-MB Ed. 3, April 2001 ...
Page 137
... Figure 59. Rx Terminal Port Parallel 19.44 Mbyte/s SONET FORMAT Example DATA SHEET (POH) (POH) C1 INVPCK = "0" INVPCK = "1" C1 J1,1 HI-Z HI-Z HI-Z HI-Z HI-Z IF ENABLED1 HI-Z J1 TIME HI-Z HI-Z - 137 of 196 - PHAST-1 TXC-06101 (POH ENABLED V1,1,1 D1 HI-Z HI-Z V1 TIME HI-Z HI-Z HI-Z TXC-06101-MB Ed. 3, April 2001 ...
Page 138
... RSPE RSYN Figure 61. Rx Terminal Port Serial Datacom Format DATA SHEET (POH) C1,2 C1 lsb C1 TIME - 138 of 196 - PHAST-1 TXC-06101 (POH) (POH PRESENT LSB. RSPE is POH (Vx,1) msb lsb ENDCMPOH = "1" ENDCMPOH = "0" Time (IF V1 Time & IF ENABLED) TXC-06101-MB Ed. 3, April 2001 ...
Page 139
... TTDI w/ TDDLY = 0 lsb TTDI w/ TDDLY = 1 lsb Figure 62. Tx Terminal Port Serial Datacom Format DATA SHEET C1 TIME ENDCMPOH = "1" ENDCMPOH = "0" C1 TIME J1 Time (IF V1 Time & IF ENABLED) - 139 of 196 - PHAST-1 TXC-06101 POH BYTES msb lsb msb lsb TXC-06101-MB Ed. 3, April 2001 ...
Page 140
... Figure 63. Rx Terminal Port Parallel 6.48 Mbyte/s Datacom Format DATA SHEET C1 TIME C1 TIME (DISPCKG = "0" & ENDCMPOH = "0") (DISPCKG = "0" & ENDCMPOH = "1") (DISPCKG = "1") - 140 of 196 - PHAST-1 TXC-06101 POH (Vx,1) ENDCMPOH = "1" ENDCMPOH = "0" Time (IF V1 Time & IF ENABLED) TXC-06101-MB Ed. 3, April 2001 ...
Page 141
... Figure 64. Tx Terminal Port Parallel 6.48 Mbyte/s Datacom Format DATA SHEET ENDCMPOH = "1" ENDCMPOH = "0" C1 TIME J1 Time (IF V1 Time & IF ENABLED) A2 TIME C1 TIME A1 TIME A2 TIME DISPCKG = "0", ENDCMPOH = "1" DISPCKG = "0", ENDCMPOH = "0" DISPCKG = "1" - 141 of 196 - PHAST-1 TXC-06101 POH C1 TIME POH TXC-06101-MB Ed. 3, April 2001 ...
Page 142
... RSYN TPARO NOTE: POH BYTES USUALLY NOT ALIGNED IN ADJACENT TIME SLOTS Figure 65. Rx Terminal Port Parallel 19.44 Mbyte/s Datacom Format DATA SHEET C1,2 C1,3 (POH ENDCMPOH = "1" ENDCMPOH = "0" TIME - 142 of 196 - PHAST-1 TXC-06101 (POH) (POH ENABLED TXC-06101-MB Ed. 3, April 2001 ...
Page 143
... DATA SHEET ENDCMPOH = "1" C1,1 C1,2 C1,3 J1,1 J1,2 J1,3 ENDCMPOH = "0" A2,3 C1,1 C1,2 C1,3 POH POH A2,2 A2,3 C1,1 C1,2 C1,3 POH - 143 of 196 - PHAST-1 TXC-06101 and IF ENABLED NOT VI or NOT ENABLED POH POH POH TXC-06101-MB Ed. 3, April 2001 ...
Page 144
... RRFI RXFR RTCO BYTE (C1+1) RTDO msb lsb msb RSPE RSYN Figure 67. Rx Terminal Port SPE-only Format DATA SHEET lsb msb lsb 30 BIT TIMES - 144 of 196 - PHAST-1 TXC-06101 J1 msb lsb msb lsb J1 Time IF V1 TIME & IF ENABLED TXC-06101-MB Ed. 3, April 2001 ...
Page 145
... E1 Byte Identifier LTFR - E2 Byte Identifier TAP/TTS - K1, K2 Byte Strobe in OW/APS Mode A1 Byte Identifier in All TOH Mode - 145 of 196 - PHAST-1 TXC-06101 68 depicts spac- J1 lsb msb lsb J1 Time IF V1 TIME & IF ENABLED -K / TOH X X 1.728 MHz in All TOH Mode TXC-06101-MB Ed. 3, April 2001 ...
Page 146
... LSB. SRFR and LRFR are used to identify the E1 and E2 Bytes, 1 FRAME (125 µS) K1 Figure 69. Rx OW/APS Port -K / TOH Port. STFR and LTFR are output on the Rising Edge FRAME (125 µ Figure 70. Tx OW/APS Port - 146 of 196 - PHAST-1 TXC-06101 ALTOW = "0" ALTOW = "1" E2 ALTOW = "0" ALTOW = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 147
... OTCO OTDI STFR LTFR TTS DATA SHEET 1 FRAME (125 µ ALTOW = "1" ALTOW = "0" Figure 71. Rx All TOH Port 1 FRAME (125 µ ALTOW = "1" ALTOW = "0" Figure 72. Tx All TOH Port - 147 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 148
... Tx Line DCC Port LTCO - 576 kHz Clock LTDI - Input Data (serial, D4-D12 Bytes) Tx POH Port Pins PTCO - 576 kHz Clock PTDI - Input Data TPS - J1 Byte Identifier 1 FRAME (125 µS) msb lsb Figure 73. Rx POH Port - 148 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 149
... FRAME (125 µS) msb lsb Figure 74. Tx POH Port RGDI - ROW 2 ROW 3 ROW 4 ROW ERR ERR Figure 75. Rx and Tx Ring Ports - 149 of 196 - PHAST-1 TXC-06101 Z5 Tx Ring Port Pins Data Input = 648 kHz, nominal ROW 6 ROW 7 ROW 8 TXC-06101-MB Ed. 3, April 2001 ...
Page 150
... ISCOCO ISCODO C1 B1 ISCOFO DATA SHEET ISCOCO - 1.408 MHz Clock (a gapped 1.728 MHz clock) ISCODO - Output Data ISCOFO - Frame Pulse 1 FRAME (125 µ Figure 76. ISC Port Input 1 FRAME (125 µ 150 of 196 - PHAST-1 TXC-06101 Output Pins TXC-06101-MB Ed. 3, April 2001 ...
Page 151
... The accumulated B2 byte must match the received B2 byte following the second valid A1/A2 pattern received. A mismatch causes the framer to go out of frame and begin searching for a new fram- ing pattern at the bit just after the subsequent A1/A2 position. DATA SHEET Figure 77. ISC Port Output - 151 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 152
... Table 8. Debounced TOH Locations - 152 of 196 - PHAST-1 TXC-06101 Byte Location C1 01C[H] F1 01D[H] D3 007[H] H3 013[H] K2 01F[H] D6 00A[H] D9 00D[H] D12 010[H] E2 019[H] Debounced Value 05A[H] 05B[H] 05C[H] 05D[H] 05E[H] 05F[H] TXC-06101-MB Ed. 3, April 2001 ...
Page 153
... B2 calculation is performed after unscrambling and excludes the nine Section Bytes. The number of received errors (including zero) is made available to the Transmit Side and to the Ring Port for use as a Line FEBE. DATA SHEET - 153 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 154
... B2 EBER alarm cleared. The number of errors per block must be less this value to be considered an error free block (range 1 to N). B2MULT B2SET 154 of 196 - PHAST-1 TXC-06101 B2SCV B2CLR B2CCV line error rates. The recom- under random error conditions and will TXC-06101-MB Ed. 3, April 2001 ...
Page 155
... Probability of Mean time to clear alarm in a window (sec) 1.00 1.00 1.00 0.99 0.66 0.03 0.025 0.024 0.020 0.020 - 155 of 196 - PHAST-1 TXC-06101 Probability of clear in a window 1.00 1.00 1.00 -3 Probability of clear in a window 0.03 0.53 1.00 1.00 -4 TXC-06101-MB Ed. 3, April 2001 ...
Page 156
... J1 Byte to be written at address 080[H], with subsequent bytes being stored in succeeding locations. DATA SHEET 4. Path AIS - RAIS-P (SR0; 0F0/1/4[H], Bit 5) 5. Pointer Increment 6. Pointer Decrement Byte Location J1 080[H] - 0BF[H] B3 0C0[H] C2 0C1[H] G1 0C2[H] F2 0C3[H] H4 0C4[H] Z3 0C5[H] Z4 0C6[H] Z5 0C7[H] Table 12. Received POH Locations - 156 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 157
... Remote Defect 2 Remote Server Defect 2 Remote Connectivity Defect 1 Remote Defect Table 14. RDI-P Format - 157 of 196 - PHAST-1 TXC-06101 Debounced Value 0D1[H] 0D3[H] 0D5[H] 0D6[H] 0D7[H] Alarm Bit Affected RRDI-P RRDI-P (PD, SD and CD) RRDI-PPD RRDI-P RRDI-P RRDI-PSD RRDI-PCD RRDI-P TXC-06101-MB Ed. 3, April 2001 ...
Page 158
... Minimum number of blocks with errors < B3CCV in window B3WIN, to declare B3 EBER alarm clear. The number of errors per block must be less this value to be considered an error free block (range 1 to N). B3MULT B3SET 158 of 196 - PHAST-1 TXC-06101 B3SCV B3CLR B3CCV TXC-06101-MB Ed. 3, April 2001 ...
Page 159
... Counter overflow is indicated by RPFEBEOF (SR7; 0F6[H], Bit 4). DATA SHEET Probability of Mean time to clear alarm in a window (sec) 1.00 1.00 0.99 0.88 0. 0.352 0.255 0.129 - 159 of 196 - PHAST-1 TXC-06101 16 give the Probability of clear in a window 0.25 0.99 1.00 -5 TXC-06101-MB Ed. 3, April 2001 ...
Page 160
... RLOP Declared / & RAIS-P Declared Inhibit B3 and / & RPNEW Declared / & RRDI-P(xx) Declared / & RLOM Declared / & B3EBER Declared / & C2UNEQ Declared / & C2MIS Declared / RPDI-P Declared & - 160 of 196 - PHAST-1 TXC-06101 & Pointer Counters FEBE-P Counters TXC-06101-MB Ed. 3, April 2001 ...
Page 161
... E1 038[H] 025[H] D2 026[H] 031[H] H2 032[H] 035[H] K1 03E[H] 028[H] D5 029[H] 02B[H] D8 02C[H] 02E[H] D11 02F[H] 03A[H] Z2 03B[H] - 161 of 196 - PHAST-1 TXC-06101 1 where: + rep- Byte Location C1 03C[H] F1 03D[H] D3 027[H] H3 033[H] K2 03F[H] D6 02A[H] D9 02D[H] D12 030[H] E2 039[H] TXC-06101-MB Ed. 3, April 2001 ...
Page 162
... TXC-06101 RCLK="0" & TTOHEN="0" Control="0" Control="1" Line Insert Line Insert Line Insert Line Insert Line Insert Line Insert 3 2,7 3 Line Insert Line Insert Line Insert Line Insert Line Insert Line Insert Line Insert TXC-06101-MB Ed. 3, April 2001 ...
Page 163
... When re-timing is disabled, termination of AIS-P will consist of removing the "1" forcing function. When the conditions are such that a Path AIS will be inserted (if enabled by RRAIS) it will be indicated by RPAISC (SR8; 1F6[H], Bit 3). DATA SHEET Byte Location (B3) 0C8[H] C2 0C9[H] G1 0CA[H] F2 0CB[H] Z3 0CD[H] Z4 0CE[H] Z5 0CF[H] - 163 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 164
... Overhead Distribution and Overhead Processing. The Tx Terminal Port routes the C1, B1, E1, F1, D1, D2, D3, B2, K1, K2, D4, D5, D6, D7, D8, D9, D10, D11, D12, Z1, Z2 and E2 Bytes to the ISC Port if SPE-only Mode is not enabled. DATA SHEET - 164 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 165
... V1 indicator at TSYNI/O and inserting its value in the two LSB’s of H4, although its initial value will be arbitrary. If DFRI/DFRI is lost the operation will not be disturbed and the same V1 alignment will be main- tained. DATA SHEET 57 - 165 of 196 - PHAST-1 TXC-06101 and 60. The V1 portion of 64 and 66. The V1 por- TXC-06101-MB Ed. 3, April 2001 ...
Page 166
... E1 118[H] 105[H] D2 106[H] 111[H] H2 112[H] 115[H] K1 11E[H] 108[H] D5 109[H] 10B[H] D8 10C[H] 10E[H] D11 10F[H] 11A[H] Z2 11B[H] Table 20. Terminal TOH Locations - 166 of 196 - PHAST-1 TXC-06101 Byte Location C1 11C[H] F1 11D[H] D3 107[H] H3 113[H] K2 11F[H] D6 10A[H] D9 10D[H] D12 110[H] E2 119[H] TXC-06101-MB Ed. 3, April 2001 ...
Page 167
... The errors are accumulated in the Roll Over counter designated Tx B3 Error Count (1D4[H]). There is no overflow indicator. DATA SHEET Byte Location J1 180[H] - 1BF[H] B3 1C0[H] C2 1C1[H] G1 1C2[H] F2 1C3[H] H4 1C4[H] Z3 1C5[H] Z4 1C6[H] Z5 1C7[H] Table 21. Terminal POH Locations - 167 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 168
... PHAST-1 TXC-06101 2 where: TLOC Declared TLOS Declared TFE Declared TSEF Declared TLOF Declared Inhibit B1 Counter TTE1 Declared TAIS-L Declared Inhibit B2 and Pointer Counters TNPTR Declared TCPTR Declared TLOP Declared TAIS-P Declared Inhibit B3 Counter TXC-06101-MB Ed. 3, April 2001 ...
Page 169
... Table DATA SHEET Byte Location J1 180[H] - 1BF[H] (B3) 1C8[H] C2 1C9[H] G1 1CA[H] F2 1CB[H] H4 1CC[H] Z3 1CD[H] Z4 1CE[H] Z5 1CF[H] Note: Used for Insert if TPATH = "1" Table 22. Tx Insert POH Locations 23 presents the available options for Transmit POH. - 169 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 170
... Table 23. Tx Line POH Options - 170 of 196 - PHAST-1 TXC-06101 TPATH="1" Control="1" Tx POH Port J1 Bytes Calculated Value Tx POH Port C2 Bytes Tx POH Port G1 Bytes Tx POH Port F2 Bytes 3 µPro H4 Bytes 3 Tx POH Port Z3 Bytes Tx POH Port Z4 Bytes Tx POH Port Z5 Bytes TXC-06101-MB Ed. 3, April 2001 ...
Page 171
... All other locations contain values written by the µPro or external values from the Tx TOH Port. In the OW/APS Mode, only the E1, E2, K1 and K2 Bytes may be externally created. In All TOH Mode, all TOH Bytes except B1, B2, H1, H2 and H3 may be externally generated. DATA SHEET - 171 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 172
... TRFRM = "1" Tx C1/J0 Selection Controls J0EN0, J0EN1, TXC1EXT (CR14; 1FE[H], Bit 6), TRC1(CR9; 1F9[H], Bit 6),and OA are used to con- trol the C1 Selection. J0ENx selects the Insert Location as shown in Table 25. If J0EN1 = "1" the Insert loca- tions consist of a 64-Byte RAM segment. Microprocessor access to these locations is by means of Locations 180[H] - 1BF[H], and is controlled by J0RWEN. When the Multiple Byte J0 messages are input via the TOH Port, the storage method is controlled by J0ENx. When J0EN(1,0) = " ...
Page 173
... TRE1 = "1" & TXE1EXT = "0" - 173 of 196 - PHAST-1 TXC-06101 External SPE-only Mode selected & TXC1EXT = "1" & "0" + TRC1 = "1" & TXC1EXT = "1" & "0" External SPE-only Mode selected & TXE1EXT = "1" + TRE1 = "1" & TXE1EXT = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 174
... C1J1EN = "1" + TXRTM = "1" +TCLK = "1" - 174 of 196 - PHAST-1 TXC-06101 External SPE-only Mode selected & TXF1EXT = "1" & "0" + TRF1 = "1" & TXF1EXT = "1" & "0" External SPE-only Mode selected & TXSDEXT = "1" + TRSD = "1" & TXSDEXT = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 175
... TXLDEXT = "0" + TRLD = "1" & TXLDEXT = "0" - 175 of 196 - PHAST-1 TXC-06101 External SPE-only Mode selected & EXAPS = "1" & "0" + TRAPS = "1" & EXAPS = "1" External SPE-only Mode selected & TXLDEXT = "1" + TRLD = "1" & TXLDEXT = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 176
... OA = "1" - 176 of 196 - PHAST-1 TXC-06101 External SPE-only Mode selected & TXZ1EXT = "1" & "0" + TRZ1 = "1" & TXZ1EXT = "1" & "0" External SPE-only Mode selected & TXZ2EXT = "1" & "0" + TRZ2 = "1" & TXZ2EXT = "1" & "0" TXC-06101-MB Ed. 3, April 2001 ...
Page 177
... If the conditions are such that a PAIS will be inserted (if enabled by TRAIS), this will be indicated by the setting of TPAISC. DATA SHEET Insert Location µPro SPE-only Mode selected & TXE2EXT = "0" + TRE2 = "1" & TXE2EXT = "0" - 177 of 196 - PHAST-1 TXC-06101 External SPE-only Mode selected & TXE2EXT = "1" & "0" + TRE2 = "1" & TXE2EXT = "1" TXC-06101-MB Ed. 3, April 2001 ...
Page 178
... RLCI and RLDI. This is controlled by LINLOOP (CR17; 1DD[H], Bit 2). DATA SHEET RX TOH PROCESSOR GENERATOR TRLOOP LPAISEN FORCE LPAISSEL AIS TX TOH GENERATOR PROCESSOR Figure 78. Loopbacks - 178 of 196 - PHAST-1 TXC-06101 RX RX TERMINAL TERMINAL PORT RTLOOP TX TERMINAL TX TERMINAL PORT TXC-06101-MB Ed. 3, April 2001 ...
Page 179
... RST is returned to the High Level. When activated, the reset process will: 1. Reset all Counters 2. Reset all Control Registers 3. Clear All Status Bits 4. Re-center the FIFOs 5. Set HWRST (SR1; 0F2/3/5[H], Bit 0) 6. Set INT (SR1; 0F2/3/5[H], Bit 7) DATA SHEET - 179 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 180
... RAMTSTEN (CR6; 0FE[H], Bit 6) is provided to allow memory testing. When it is set to "1" RAM access by all internal operations is inhibited. Two controls: TEST1 and TEST2 (CR17; 1DD[H], Bits 4 and 3) are used for Internal TXC tests. These must be set to "0" for normal operation. All Counters clear on Read. Writing to a 16-Bit Counter is accomplished by first writing the HIBYTE Location (1FF[H]) then writing to the Lower Order Register ...
Page 181
... TIEN, PIEN and DIEN enable categories of events for interrupt creation. These three controls are discussed below. DATA SHEET - 181 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 182
... Tx Terminal Pointer Tracking Tx Terminal Pointer Tracking Table 26. Transport Layer Events - 182 of 196 - PHAST-1 TXC-06101 -VE Control Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes No TXC-06101-MB Ed. 3, April 2001 ...
Page 183
... Line Timing Gen. Line Timing Gen. Line Timing Gen. Tx Re-timing FIFO Tx Ring Port Table 28. Device Layer Events - 183 of 196 - PHAST-1 TXC-06101 -VE Control Yes Yes Yes Yes Yes Yes -VE Control Yes Yes Yes No No Yes No Yes Yes Yes Yes TXC-06101-MB Ed. 3, April 2001 ...
Page 184
... The pin TEST is a control that when taken Low, with RST held Low, will force all output and bidirectional pins to a high impedance state. TEST at the Low Level by itself invokes a TXC Device Test Mode. For normal opera- tion TEST must be at the High Level. ...
Page 185
... CORE LOGIC OF PHAST-1 DEVICE Instruction Register Test Data Registers TAP Controller TDI TDO TCKI TMSI TRESI Control Pins IN OUT Boundary Scan Serial Test Data Figure 79. Boundary Scan Schematic - 185 of 196 - PHAST-1 TXC-06101 Signal input and output pins TXC-06101-MB Ed. 3, April 2001 ...
Page 186
... SEE DETAIL “A” DEGREE Note: This package complies with JEDEC Publication 95, Specification MS-026. All linear dimensions are in millimeters. Figure 80. PHAST-1 TXC-06101 144-Pin Low Profile Plastic Quad Flat Package DATA SHEET 73 72 TRANSWITCH TXC-06101AILQ 37 36 17.50 (SQ) 20.00 0.10 (SQ) 22.00 0.10 (SQ) ...
Page 187
... Figure 82. Asynchronous DSX-1 Mapped to OC-1 Ring-Protected Application DATA SHEET 28 DS1s RDATA(4-1) DS1MX7 QT1F- Plus TDATA(4-1) RSIGL(4-1) TXC-03103 TXC-04201B TSIGL(4- Proc. System RING PORT PHAST-1 TXC-06101 ( LIU QT1M LIU TXC-04251 187 of 196 - PHAST-1 TXC-06101 STS-1 PHAST-1 Line LIU TXC-06101 OC DSX DSX-1 28 TXC-06101-MB Ed. 3, April 2001 ...
Page 188
... Proprietary TranSwitch Corporation Information for use Solely by its Customers ORDERING INFORMATION Part Number: TXC-06101AILQ RELATED PRODUCTS TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator single device, it provides the SONET interface to any payload. It provides access to all of the transport and path overhead defined for an STS-1/STS-N SONET signal. This device has ...
Page 189
... Web: www.atmforum.com Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel Fax Web: www.etsi.org - 189 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 190
... Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp - 190 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 191
... Added last sentence to Rx-Tx Terminal Loopback subsection. 189 Updated Standard Documentation Sources section. 191 Updated List of Data Sheet Changes section. DATA SHEET Edition 3, April 2001 PRELIMINARY Edition 2, June 2000 Summary of Change with t and t PWL PWH - 191 of 196 - PHAST-1 TXC-06101 with TXC-06101-MB Ed. 3, April 2001 ...
Page 192
... Proprietary TranSwitch Corporation Information for use Solely by its Customers - NOTES - - 192 of 196 - DATA SHEET PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 193
... Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or DATA SHEET - NOTES - - 193 of 196 - PHAST-1 TXC-06101 TXC-06101-MB Ed. 3, April 2001 ...
Page 194
... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - 194 of 196 - • • Fax: 203-926-9453 www.transwitch.com ...
Page 195
... Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453 e-mail (info@txc.com telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www ...
Page 196
... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...