TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 133

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

LINE FORMATS
The Line Formats for the PHAST-1 are designed for use in two applications. The first is for use in a native STS-
1 Environment. The second is for use in a situation where the PHAST-1 is preceded, on the Line Side, by addi-
tional circuitry such as an STS-1 to STS-N multiplexer. The choice of applications is controlled by STS1 (CR2;
0FA[H], Bit 7). When set to "1", the Line Side signals are treated as an STS-1.
Rx Line Port Format
The inputs at the Rx Line Port are RLDI, RFRI, RLCI and RXLOS. RLDI and RFRI are clocked in on the Rising
Edge of RLCI. RXLOS is an optional asynchronous input from an external LOS detector.
If STS1 = "1":
If STS1 = "0":
Tx Line Port Format
If STS1 = "1"
If STS1 = "0"
The Tx Line Port Outputs are TLDO and TLCO, where TLDO is clocked out on the Falling Edge of TLCO. The
relationship between TLCO, TLDO and the reference inputs used by the LTG is shown in Figure 53. When
External Transmit Timing is employed the MSB of the A1 Byte on TLDO occurs 3½ bit times after TFRI is sam-
pled. If Terminal Timing is employed the MSB of the A1 Byte is as follows:
Serial SONET
Datacom Mode, PARA = "0"
Datacom Mode, PARA = "1"
TDDLY is (CR12; 1FC[H], Bit 0).
1. Full framing is performed using the A1 and A2 Bytes and RFRI is ignored.
2. The B1 Errors are calculated using the B1 Byte.
3. Unscrambling is performed.
1. The input RFRI is enabled and a partial framing algorithm is employed where the A1 and A2 Bytes
2. The content of the B1 Byte is interpreted as a count of B1 Errors.
3. Unscrambling is not performed.
1. B1 Parity is calculated and placed in the B1 Byte.
2. Scrambling is performed.
1. The outgoing B1 Byte contains a mask that can be used to create B1 Parity errors.
2. Scrambling is not performed.
1. C1J1EN = "0" -
2. C1J1EN = "1" -
1. TDDLY = "0"
2. TDDLY = "1"
1. TDDLY = "0"
2. TDDLY = "1"
are used to verify the frame position defined by RFRI.
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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22½ bit times after the MSB of the A1 Byte input at TTDI is sampled by TTCI/O
6½ bit times after the Rising Edge of TSYNI/O and the Falling Edge of
TSPEI/O is sampled by TTCI/O
7½ bit times after DFRI is sampled by DRCI
10½ bit times after DFRI is sampled by DRCI
12 bit times after DFRI is sampled by DRCI
20 bit times after DFRI is sampled by DRCI
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DATA SHEET
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1