TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 151

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
PHAST-1
DATA SHEET
TXC-06101
Figure 77. ISC Port Output
RX TOH PROCESSING
The Rx TOH Processing Block is responsible for Framing, De-scrambling (if STS1 = "1"), Overhead Distribu-
tion, Overhead Processing and Pointer Tracking. As discussed in the section "Rx Line Port Format," the exter-
nal inputs are RLDI (data), RLCI (clock), RFRI (frame) and RXLOS (LOS Input). When used, RFRI consists of
an active Low Pulse during the MSB Time of the C1 Byte. RLCI, RLDI and RFRI are monitored for presence.
An absence of transitions is reported as RLOC (SR0; 0F0/1/4[H], Bit 7), RLOS (SR0; 0F0/1/4[H], Bit 0) and
RLFRI (SR3; 0E8/9/C[H], Bit 7), respectively. As previously discussed, external access to the Rx TOH Bytes is
available at the Rx E
-K
/ All TOH Port, the Rx Section DCC Port and the Rx Line DCC Port.
X
X
Framing
The Framing portion detects Framing Errors - RFE (SR3; 0E8/9/C[H], Bit 6), Severely Errored Frame - RSEF
(SR0; 0F0/1/4[H], Bit 1) and Loss of Frame - RLOF (SR0; 0F0/1/4[H], Bit 2). The Framer is a full off Line syn-
chronizer, i.e., upon declaration of RSEF the previous frame alignment will be maintained until frame acquisi-
tion is completed and RSEF cleared. The framing algorithm used, when STS1 = "1", meets the Bellcore
-3
requirement that a BER of 10
, assuming a Poisson distribution of bit errors, will not cause an RSEF more
than once in six minutes. If STS1 = "0" it is assumed that there is a framing device (such as an STS-N Multi-
plexer) between the PHAST-1 and the Line. The upstream device may provide the signal RFRI, which is used
to set the Frame Delineation Counters to the appropriate value such that the subsequent A1 and A2 Bytes may
be detected at the expected positions in the required time.
When control bit B2FREN is set to 1 (CR6; 0FE[H], Bit 7) a B2 check is made before declaring in frame. This
can be used when handling payloads that may contain a framing pattern after scrambling that could mimic the
true framing pattern. The accumulated B2 byte must match the received B2 byte following the second valid
A1/A2 pattern received. A mismatch causes the framer to go out of frame and begin searching for a new fram-
ing pattern at the bit just after the subsequent A1/A2 position.
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TXC-06101-MB
Ed. 3, April 2001