TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 128

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

There are two additional Tx Terminal Port Modes that are invoked when SONET Mode is selected. These are
C1J1 Mode and Framing Mode. They are controlled by C1J1EN (CR6; 0FE[H], Bit 1). When set to "1", Frame
Delineation is accomplished with the signals TSYNI/O and TSPEI/O. When set to "0", the incoming A1/A2 and
H1/H2 Bytes are used to determine Frame and SPE alignment.
TIMING GENERATORS
The PHAST-1 contains two timing generators. They are the Terminal Timing Generator and the Line Timing
Generator. These reside in the Receive Side and Transmit Side, respectively (see Figure 14).
Terminal Timing Generator
The Terminal Timing Generator (TTG) creates the signals required for the Rx Re-timing FIFO (when Receive
Re-timing is enabled), the Rx Terminal Generator and the Rx Terminal Port. The external inputs to the TTG are
the pins RRCI and RRFI/RRFI. RRFI/RRFI is active High when RRCI is 6.48 or 19.44 MHz and active Low
when RRCI is 51.84 MHz. The use of RRFI/RRFI is optional in the 6.48 Mbyte/s and 51.84 Mbyte/s modes, but
is required in the 19.44 Mbyte/s mode. If a frame pulse is not supplied, the start of the frame generated at the
Rx Terminal Port will be arbitrary. If it is not used, RRFIEN (CR3; 0FB[H], Bit 7) should be set to "0" to prevent
alarm generation. When employed, the generated frame will track the reference frame. If RRFI/RRFI fails, the
alignment of the generated frame will be maintained. Any change in position of RRFI/RRFI is reported as Rx
Reference Change of Frame Alignment - RRCOFA (SR4; 1F2/3/5[H], Bit 7). The Loss Of Rx Reference (RRCI
and/or RRFI/RRFI) is reported as LORR (SR4; 1F2/3/5[H], Bit 6).
When External Rx Timing is enabled, RRCI must be 51.84 MHz when serial outputs are desired at the Rx Ter-
minal Port. If 6.48 Mbyte/s parallel output is desired, then RRCI may be either 51.84 MHz or 6.48 MHz. The
combination of RRCI and RRFI, where RRCI is 19.44 MHz, must be used when the Rx Terminal Port is operat-
ing in parallel mode at 19.44 Mbyte/s. In addition to the external signals mentioned above, the TTG may also
utilize internal signals generated by the Rx TOH Processor. These internal signals are referred to as RXCK
(51.84 MHz clock) and RXFR (frame). This latter combination may only be used for 51.84 Mbit/s serial and
6.48 Mbyte/s parallel output modes. The availability of internal or external inputs to the TTG provides two
Receive Timing Modes: Line Timing or External Rx Timing.
Reference Clock selection is controlled by RCLK (CR10; 1FA[H], Bit 5), RETSEL (CR16; 0FF[H], Bit 7) and the
Pin MBEI. The settings for these controls are given in Table 2. RCLK determines whether Line Timing or Exter-
nal Rx Timing is employed. When External Receive Timing is selected (RCLK = "1"), RETSEL Selects Parallel
or Serial Reference sets for 6.48 MHz. Parallel Reference is selected when RETSEL = "0". MBEI, when Low,
selects 19.44 MByte/s operation. In those configurations where RXCK or RRCI at 51.84 MHz are selected,
both serial and 6.48 Mbyte/s parallel outputs are active.
Pin MBEI
High
High
High
High
High
Low
Low
Proprietary TranSwitch Corporation Information for use Solely by its Customers
SPE
0
0
0
0
1
-
-
DATACOM
Table 1. Primary Operating Modes
0
1
0
0
1
1
-
- 128 of 196 -
PARA
DATA SHEET
0
1
0
1
0
-
-
Parallel SONET - 6. 48 Mbyte/s
Parallel Datacom - 6. 48 Mbyte/s
Parallel SONET - 19.44 Mbyte/s
Parallel Datacom - 19.44 Mbyte/s
Serial SONET
Serial Datacom
SPE-only
P.O.M.
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1