TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 122

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

CONTROL REGISTER 15
Note 1. If B2MULT(2-0) = "110" or "111", control is disabled and Bit Equal to "0" condition applies.
Address
1DF
[H]
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
TLFEBEEN Line FEBE Enable:
TXLD-EXT Tx D4-D12 Bytes External Con-
TSWRES
INHTB1C
INHTB2C
B2ELRDI
Symbol
STLRDI
TTEAIS
trol: Insert Tx TOH RAM Locations
contain D4-D12 Bytes from Tx TOH
Port or Tx Section DCC Port
Tx Software Reset:
resets all Tx Side counters and
clears Tx Side Status Bits. Normal
operation is inhibited.
Tx Terminal Enable AIS:
automatic insertion of AIS-L at Tx
Line Port due to Tx Terminal Port or
Tx Alarm Port conditions enabled
Bits 5-8 of the Z2 Byte in the Tx
Line Port Data are overwritten by
FEBE-L derived from Rx B2 Byte or
Tx Ring Port value.
Inhibit Tx B1 Counter:
accumulation of B1 errors at Tx
Terminal Port inhibited.
Inhibit Tx B2 Counter:
accumulation of B2 errors at Tx
Terminal Port inhibited.
Send Tx Line RDI:
RDI-L inserted in Tx Line Port out-
put data.
B2 Excess BER Line RDI Enable:
Excess B2 Error condition included
in equation for RDI-L insertion at
Tx Line Port.
RING
DISRLAL
TLFEBEEN
RGFEBE-L
Value
FEBE-L from
Rx B2 Err
Source Z2
Byte, Bits 5-8
Bit Equal to "1"
=1
=0
=1
Tx Line FEBE-L Insertion
- 122 of 196 -
/
DATA SHEET
&
&
/
Conditions
&
+
&
Insert Tx TOH RAM Locations for
D4-D12 Bytes written by µPro
terminates Tx Side Reset. Normal
operation resumed.
automatic insertion of AIS-L at Tx
Line Port due to Tx Terminal Port or
Tx Alarm Port conditions disabled
Bits 5-8 of the Z2 Byte in the Tx
Line Port Data are not overwritten.
accumulation of B1 errors at Tx
Terminal Port enabled.
accumulation of B2 errors at Tx
Terminal Port enabled.
insertion of RDI-L at Tx Line Port
Data not forced.
Excess B2 Error condition
excluded from equation for RDI-L
insertion at Tx Line Port.
+
Tx Line Z2 Byte
Bits 5-8
Bit Equal to "0"
& = Logical AND
+ = Logical OR
/ = Logical NOT
= = Control State
LEGEND
See TRLD and
LDCCEN.
See TRLRDI.
Note 1
See TRLRDI.
Comments
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1