TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 179

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Tx-Rx Line Loopback
Tx-Rx Line Loopback disconnects the RLDI and RLCI Inputs and substitutes the Tx TOH Generator Clock and
Data outputs. When Tx-Rx Line Loopback is initiated RFRI is disregarded. This Loopback is controlled by
TRLOOP (CR0; 0F8[H], Bit 0).
When a Tx-Rx Line Loopback is enabled the signal exiting on TLDO may be either the information that is
looped back, i.e., the information input at the Tx Terminal Port, or it may be a forced AIS signal. This is con-
trolled by LPAISEN (CR12; 1FC[H], Bit 4). When the Forced AIS option is selected LPAISSEL (CR12; 1FC[H],
Bit 3) determines if AIS-L or AIS-P is output. Termination of AIS Insertion by removing the loopback or chang-
ing the state of LPAISEN will not cause an NDF to be transmitted. AIS termination with an NDF indication can
be achieved by performing the following sequence:
Activation of Tx-Rx Line Loopback will inhibit RLFRI from creating interrupts or downstream alarms. The RLOC
and RLOS Detectors will monitor the looped signal.
Rx-Tx Terminal Loopback
Rx-Tx Terminal Loopback disconnects the path between the Tx Terminal Port and the Tx Terminal Processor
and substitutes the Rx Terminal Generator output for the Tx Terminal Port Input. Rx-Tx Terminal Loopback is
controlled by RTLOOP (CR8; 1F8[H], Bit 0). When Rx-Tx Terminal Loopback is enabled the signal at the Rx
Terminal Port is unaffected. Activation of Rx-Tx Terminal Loopback will inhibit TLOC and TLOS from creating
interrupts or upstream alarms if TTOHEN = "0". If TTOHEN = "1" during Rx-Tx Terminal Loopback, the TLOC
and TLOS circuits will monitor the terminal inputs. The looped data is not processed by the Tx terminal framer
(which continues to monitor the Tx terminal input data) but rather has a frame indicator sent with it to the Tx
Terminal Processor from the Rx side. Control bit H4INT must be set to "0" to disable the Tx multiframe genera-
tion.
RESETS
The PHAST-1 has four reset mechanisms: Hardware Reset, Software Receive Side Reset, Software Transmit
Side Reset and Chip Reset.
Hardware Reset is accomplished with the pin RST, which is active Low. This is a level sensitive input. The
device remains in the reset condition until RST is returned to the High Level. When activated, the reset process
will:
1. forcing the Tx OH Generator to Insert the appropriate AIS
2. removing the loopback or changing LPAISEN
3. Terminating the AIS Insertion at the Tx OH Generator.
1. Reset all Counters
2. Reset all Control Registers
3. Clear All Status Bits
4. Re-center the FIFOs
5. Set HWRST (SR1; 0F2/3/5[H], Bit 0)
6. Set INT (SR1; 0F2/3/5[H], Bit 7)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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DATA SHEET
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1