TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 150

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

tunity sequences will be output as all "0"s. The information content of the remaining six Segments (Rows 3 - 8)
is undefined at this time.
The Tx Ring Port information format is as described above. The first 10 bits ("1111111110") constitute a fram-
ing pattern. The frame pattern must be present for the succeeding information to be accepted. Ring port failure
is reported as LORG (SR4; 1F2/3/5[H], Bit 2). The receipt of RDI-L (PRDIL = "1") or RDI-P (PRDIL and/or
PRDIH = "1") indications at the Ring Port is reported as RGRDI-L and RGRDI-P (SR4; 1F2/3/5[H], Bits 0 and
1), respectively.
ISC PORT
The Internal Systems Communications (ISC) Port provides access to selected TOH Bytes moving to and from
the Terminal Interfaces. The bytes handled at the ISC Port are: C1, B1, E1, F1, D1, D2, D3, B2, K1, K2, D4,
D5, D6, D7, D8, D9, D10, D11, D12, Z1, Z2 and E2. Externally generated bytes that are input at the ISC Port
will, if enabled, appear in the outgoing signal at the Rx Terminal Port. Bytes entering the Tx Terminal Port will
always be output by the ISC Port. The pins of the ISC Port are given below. Clocks ISCICO and ISCOCO are
gapped during what would be the A1, A2 (which follows E2), H1, H2, and H3 (which follows D3) times.
The input operations are shown in Figure 76. Serial data (ISCIDI) is sampled on the Rising Edge and ISCIFO
is output on the Falling Edge, of ISCICO. ISCIFO occurs one and a half bit times before the MSB of the C1
Byte is sampled. ISCIDI consists of the 22 Bytes listed above. They are input in the order in which they are out-
put at the Rx Terminal Port.
The output operations are shown in Figure 77. All outputs occur on the Rising Edge of ISCOCO. ISCODO con-
sists of the 22 Bytes listed above. They are output in the order in which they are received at the Tx Terminal
Port. ISCOFO occurs one bit time before the MSB of the C1 Byte is output.
ISCICO
ISCIDI
ISCIFO
ISCICO
ISCIDI
ISCOCO
ISCODO
ISCIFO
ISCOFO
-
-
-
Proprietary TranSwitch Corporation Information for use Solely by its Customers
msb
msb
1.408 MHz Clock
(output, a gapped 1.728 MHz clock)
Input Data
Frame Pulse (output)
C1
C1
Input Pins
lsb
lsb
B1
B1
E1
E1
Figure 76. ISC Port Input
F1
F1
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1 FRAME (125 µS)
1 FRAME (125 µS)
DATA SHEET
ISCOCO
ISCODO
ISCOFO
D1
D1
-
-
D2
D2
-
1.408 MHz Clock
Output Data
Frame Pulse
(a gapped 1.728 MHz clock)
D3
D3
Output Pins
Z1
Z1
Z2
Z2
E2
E2
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1