TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 125

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

CONTROL REGISTER 18
Notes:
1. If J0EN1 = "0" the Rx Line C1/J0 RAM Location is 01C[H] and the C1/J0 Tx Insert RAM Location is 13C[H].
2. If J0EN1 = "1" the Rx Line J0 Message RAM locations are accessed at 080[H] - 0BF[H] and the J0 Message Tx Insert
Address
1DC
RAM Locations are accessed at 180[H] - 1BF[H]. (J0RWEN must be set to access these J0 bytes.)
[H]
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
J0RWEN J0 Read/Write Enable: J0 Bytes
J0MLRDI J0 Mismatch Line RDI Enable:
CHPRES Chip Reset:
J0MLAIS J0 Mismatch Line AIS Enable:
TMBSEL1
TMBSEL0
Symbol
J0EN1
J0EN0
accessed by µPro at addresses
080[H] - 0BF[H] (Rx Port J0 RAM
Location) and 180[H] - 1BF[H] (Tx
J0 Insert RAM Location)
J0 Mismatch condition included in
equation for RDI-L insertion at Tx
Line Port
J0 Mismatch condition included in
equation for AIS-L insertion at Rx
Terminal Port
J0 Enable(1,0): selects the J0 processing configuration
J0EN1
Tx Multiplex Bus Select (1,0): determines time slot assignment in 19.44
Mbyte/s modes for Tx Terminal Port.
TMBSEL1
Acts like pin RST except that con-
trol registers and µPro interface are
not affected. Normal operation is
inhibited.
0
0
1
1
0
0
1
1
Bit Equal to "1"
J0EN0
0
1
0
1
TMBSEL0
0
1
0
1
- 125 of 196 -
Function
J0 processing inhibited. The Byte following A2 is
a C1 Byte.
Single Byte J0 processing: J0MIS declared if Rx
Side mismatch
16 or 64-byte message received and transmitted
with incoming message (at Rx Line Port, Tx TOH
Port, or Tx Terminal Port) stored in rotating fash-
ion with no specific starting point.
64-byte message received and transmitted with
incoming message (at Rx Line Port, Tx TOH
Port, or Tx Terminal Port) stored such that the
byte following ASCII (CR) and (LF) characters is
stored in the Lowest address location
DATA SHEET
Conditions
Time Slot
MBSEL(1,0) assignments used
First
Second
Third
J1 Bytes accessed by µPro at
addresses 080[H] - 0BF[H] (Rx
Port J1 RAM Location) and 180[H]
- 1BF[H] (Tx J1 Insert RAM Loca-
tion)
J0 Mismatch condition excluded
from equation for RDI-L insertion at
Tx Line Port
J0 Mismatch condition excluded
from equation for AIS-L insertion at
Rx Terminal Port
Terminates chip reset. Normal
operation is resumed
Bit Equal to "0"
effective only if
J0EN(1,0) =
"01"
See TRLRDI.
effective only if
J0EN(1,0) =
"01"
Notes 1, 2
See J0RWEN,
TRC1 and
TXC1EXT.
effective only if
Pin MBEI is
Low
See MBSEL0
and MBSEL1
TXC-06101
Comments
Ed. 3, April 2001
TXC-06101-MB
PHAST-1