TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 88

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

STATUS REGISTER 1
Notes:
1. This is the alarm that is used to report Single Bit RDI-P . It is retained for backwards compatibility.
2. This is a short duration event (<< 1 Frame). The µPro may not be able to read the unlatched value.
Address
0F2
0F3
0F5
[H]
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
RBUSCOL Rx Terminal Bus Collision:
RPNEW
Symbol
RTNEW
HWRST
RRDI-P
RRDI-L
RAPS
INT
Interrupt:
any event that causes a µPro
Interrupt
Rx TOH New:
any new debounced value of C1,
F1, K1, K2, Z1 or Z2
Rx POH New:
any new debounced value of C2,
F2, Z3, Z4 or Z5
Rx RDI-P:
PRDISEL = "0" and G1, Bits 5-7
= "100" or "111" for 10 consecu-
tive Frames
PRDISEL = "1" and G1, Bits 5-7
= "100" or "111" for 5 consecutive
Frames
Rx RDI-L:
K2 Byte bits 6, 7 and 8 = "110" for
5 consecutive frames
Rx APS Fail:
12 frame sliding window that
does not contain 3 consecutive,
identical pairs of K1 and K2 Bytes
TPDVO Low and either TPDVI0
or TPDVI1 Low at the clock edge
upon which data is output.
Hardware Reset:
Hardware reset via pin RST
Enter
- 88 of 196 -
DATA SHEET
Conditions
No Exit Conditions - Latched Val-
ues are reset by µPro Read of
0F2[H] or Writing "1" to this bit in
0F3[H].
No Exit Conditions - Latched Val-
ues are reset by µPro Read of
0F2[H] or Writing "1" to this bit in
0F3[H].
No Exit Conditions - Latched Val-
ues are reset by µPro Read of
0F2[H] or Writing "1" to this bit in
0F3[H].
PRDISEL = "0" and G1, Bits 5-7
"100" or "111" for 10 consecutive
Frames
PRDISEL = "1" and G1, Bits 5-7
"100" or "111" for 5 consecutive
Frames
K2 Byte bits 6, 7 and 8 "110" for
5 consecutive frames
reception of 3 consecutive, identi-
cal pairs of K1 and K2 Bytes
TPDVO Low and both TPDVI0
and TPDVI1 High at the clock
edge upon which data is output.
No Exit Conditions - Latched Val-
ues are reset by µPro Read of
0F2[H] or Writing "1" to this bit in
0F3[H].
Exit
0F5, see Note 2.
inhibited if RLOC,
RLOS or RLOF is
declared or if
DISRLAL = "1"
0F5, see Note 2.
inhibited if RLOC,
RLOS, RLOF,
RAIS-L, RLOP or
RAIS-P is declared
0F5, see Note 2.
note 1
inhibited if RLOC,
RLOS, RLOF,
RAIS-L, RLOP or
RAIS-P is declared
inhibited if RLOC,
RLOS, or RLOF is
declared or if
DISRLAL = "1"
inhibited if RLOC,
RLOS, or RLOF is
declared or if
DISRLAL = "1"
0F5, see Note 2.
0F5, see Note 2.
Comments
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1