TC58NVG1S3ETA00 Toshiba, TC58NVG1S3ETA00 Datasheet
TC58NVG1S3ETA00
Specifications of TC58NVG1S3ETA00
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TC58NVG1S3ETA00 Summary of contents
Page 1
... Program/Erase time Auto Page Program 300 μs/page typ. Auto Block Erase 2.5 ms/block typ. • Operating current Read (25 ns cycle max. Program (avg max Erase (avg max 50 μA max Standby • Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) 2 PROM 1 TC58NVG1S3ETA00 2010-05-21C ...
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... TC58NVG1S3ETA00 × CLE 16 ALE I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect Ready/Busy V Power supply CC V Ground SS 2 TC58NVG1S3ETA00 × I/O8 43 I/O7 42 I/ I/O4 31 I/O3 30 I/ 2010-05-21C ...
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... This parameter is periodically sampled and is not tested for every device. Status register Address register Command register Control circuit HV generator RATING PARAMETER CONDITION OUT 3 TC58NVG1S3ETA00 V CC Column buffer Column decoder Data register Sense amp Memory cell array VALUE − 0.6 to 4.6 − 0.6 to 4.6 − 0 0.3 ( ≤ 4 ...
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... OUT mA, tcycle = OUT ⎯ ⎯ − − TC58NVG1S3ETA00 MIN TYP. MAX ⎯ 2008 2048 MIN TYP. MAX ⎯ 2.7 3.6 ⎯ + 0.3 Vcc x 0 − 0.3 * ⎯ Vcc x 0.2 MIN TYP. MAX ⎯ ⎯ ± 10 ⎯ ⎯ ± 10 ⎯ ...
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... Data Cache Busy in Page Copy (following 3Ah) DCBSYR2 t WE High to Busy WB t Device Reset Time (Ready/Read/Program/Erase) RST *1: tCLS and tALS can not be shorter than tWP *2: tCS should be longer than tWP + 8ns. PARAMETER 5 TC58NVG1S3ETA00 MIN MAX UNIT ⎯ ⎯ ⎯ ⎯ ...
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... When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling edge of /WE, and waveforms look like Extended Data Output Mode PARAMETER MIN 6 TC58NVG1S3ETA00 CONDITION V : 2.7 to 3.6V CC − 0 ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O Setup Time CLH ALH TC58NVG1S3ETA00 Hold Time 2010-05-21C ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O Data Input Cycle Timing Diagram t CLS CLE ALS ALE WE I CA0 to 7 CA8 TC58NVG1S3ETA00 PA0 to 7 PA8 CLH ALH 2111 IN 2010-05-21C t CLH ALH t DH PA16 ...
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... REA t CEA I Status Read Cycle Timing Diagram CLE t CLS I 70h represents the hexadecimal number REH RHZ RHZ t t REA t RHOH RHOH t CLR t CLH CEA t WHC t WHR 70h * 9 TC58NVG1S3ETA00 t CHZ RHZ t REA t RHOH t CEA : CHZ t RHOH t t RHZ REA Status output : 2010-05-21C ...
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... CA0 I/O 00h to 7 Col. Add ALH CA8 PA0 PA8 PA16 ALH CA8 PA0 PA8 PA16 TC58NVG1S3ETA00 t CLR t t CLS CLH ALS CEA REA D OUT 30h N Data out from Col. Add CLR t t CLS CLH ALS CEA REA D OUT 30h N Col. Add. N ...
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... CLH t t CLS CLS ALH ALS DCBSYR1 PA8 PA16 30h 31h to 15 Page address M 11 TC58NVG1S3ETA00 t t CLR t CLH t CLS tCEA DCBSYR1 REA D D OUT OUT 31h D OUT 0 1 Page address M Col. Add Continues to of next page CLR tCEA REA D OUT 0 ...
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... Continues from 1 of last page t CLR t CLH t CLS tCEA t DCBSYR1 REA D OUT OUT 31h D OUT 1 0 Page address Col. Add TC58NVG1S3ETA00 t CLR t CLH t CLS tCEA DCBSYR1 REA D D OUT OUT 3Fh D OUT Col. Add. 0 Make sure to terminate the operation with 3Fh command. ...
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... Column Address Change in Read Cycle Timing Diagram (1/2) CLE t t CLS CLH ALH ALS ALE CA0 I/O 00h ALH CA8 PA0 PA8 PA16 Page address P 13 TC58NVG1S3ETA00 t CLR t t CLS CLH tCEA t ALS REA D OUT 30h A Page address Column address A Continues from 2010-05-21C D D OUT OUT next page ...
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... CLS CLH RHW WE t ALH ALE OUT I/O 05h Continues from 1 t CLR t t CLS CLH ALS ALH ALS t WHR CA0 CA8 E0h Column address B Column address of last page 14 TC58NVG1S3ETA00 tCEA REA OUT OUT OUT N’ B Page address P B 2010-05-21C ...
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... Data Output Timing Diagram CLE CE WE ALE REH RE t CEA t REA I REA t RLOH Dout Dout RHOH 15 TC58NVG1S3ETA00 t CLS CHZ RHZ t REA t RLOH t RHOH 2010-05-21C t CLH ALH Command ...
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... CLS CLE t t CLS CLH ALH t ALS ALE CA0 CA8 80h I Column address ALH t ALS PA16 PA0 PA8 not input data while data is being output 2112 (byte input data for × 8 device). 16 TC58NVG1S3ETA00 t PROG 10h 70h IN N+1 2010-05-21C t DH Status output ...
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... Auto-Program Operation with Data Cache Timing Diagram (1/3) t CLS CLE t t CLS CLH ALH t ALS ALE CA0 CA8 I/O 80h ALH t ALS PA16 PA0 PA8 not input data while data is being output CA0 to CA11 this diagram. 17 TC58NVG1S3ETA00 t DCBSYW2 15h N+1 D 2111 IN 1 Continues next page 2010-05-21C CA0 80h to 7 ...
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... WE t ALH t ALS ALE CA0 CA8 I/O 80h Repeat a max of 62 times (in order to program pages block). 1 Continued from 1 of last page t ALH t ALS PA0 PA8 PA16 not input data while data is being output TC58NVG1S3ETA00 t DCBSYW2 15h N+1 D 2111 IN 2010-05-21C CA0 80h ...
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... PROG = t of the last page + t t PROG PROG PROG A = (command input cycle + address input cycle + data input cycle time of the last page) If “A” exceeds the t of previous page, t PROG 19 TC58NVG1S3ETA00 t PROG (* 10h 70h D 2111 IN of the previous page − ...
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... Multi-Page Program Operation with Data Cache Timing Diagram (1/4) t CLS CLE t t CLS CLH ALH t ALS ALE CA0 CA8 I/O 80h ALH t ALS PA16 PA0 PA8 N Page Address M District not input data while data is being output TC58NVG1S3ETA00 t DCBSYW1 11h 81h D 2111 IN 1 Continues next page 2010-05-21C t DH CA0 to 7 ...
Page 21
... DS DH CA0 CA8 I/O 81h Repeat a max of 63 times (in order to program pages block). 1 Continued from 1 of last page t ALH t ALS PA0 PA8 PA16 Page Address M District not input data while data is being output TC58NVG1S3ETA00 t DCBSYW2 15h N+1 D 2111 IN 2010-05-21C CA0 80h ...
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... Multi-Page Program Operation with Data Cache Timing Diagram (3/4) t CLS CLE t t CLS CLH ALH t ALS ALE CA0 CA8 I/O 80h ALH t ALS PA16 PA0 PA8 Page Address M+n District not input data while data is being output TC58NVG1S3ETA00 t DCBSYW1 11h N+1 D 2111 IN 3 Continues next page 2010-05-21C CA0 81h to 7 ...
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... Since the last page programming by 10h command is initiated after the previous cache during cache programming is given by the following equation. PROG of the last page + t of the previous page − A PROG of previous page the last page is t PROG PROG 23 TC58NVG1S3ETA00 t PROG (* 10h N+1 D ...
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... Auto Block Erase Timing Diagram CLE t CLS t CLH CLS ALS ALE PA0 PA8 60h I Auto Block Erase Setup command : ALH t WB PA16 D0h Erase Start command : Do not input data while data is being output. 24 TC58NVG1S3ETA00 t BERASE Status 70h output Busy Status Read command 2010-05-21C ...
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... Multi Block Erase Timing Diagram CLE t CLS t CLH CLS ALS ALE I/O1 PA0 PA8 60h Auto Block Erase Setup command Repeat 2 times (District-0, not input data while data is being output ALH WB BERASE PA16 D0h Busy 25 TC58NVG1S3ETA00 71h Status output Status Read command 2010-05-21C ...
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... ID Read Operation Timing Diagram t CLS CLE t CLS ALS ALH t ALH ALE I/O 90h 00h ID Read Address command 00 t CEA REA REA REA 98h DAh Maker code Device code 26 TC58NVG1S3ETA00 t t REA REA See See See Table 5 Table 5 Table 2010-05-21C ...
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... H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with an appropriate resister signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee. TC58NVG1S3ETA00 L), such as during a Program or Erase or Read after the falling edge REA ...
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... CA2 CA1 L L CA11 CA10 CA9 PA5 PA4 PA3 PA2 PA1 PA13 PA12 PA11 PA10 PA9 TC58NVG1S3ETA00 I/O1 CA0 to CA11: Column address PA0 to PA16: Page address CA0 PA6 to PA16: Block address CA8 PA0 to PA5: NAND address in block PA0 PA8 PA16 2010-05-21C ...
Page 29
... Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit * low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or read to device. Reset or Status Read command can be input during Read Busy. ALE TC58NVG1S3ETA00 * V/V CC 2010-05-21C ...
Page 30
... CLE Output select L Output Deselect First Cycle HEX data bit assignment Serial Data Input: 80h ALE TC58NVG1S3ETA00 Second Cycle Acceptable while Busy ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ ⎯ ⎯ I/O1 RE I/O1 to I/O8 L Data output H High impedance 2010-05-21C Power Active Active ...
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... E0h commands. The data is read out in serial starting at the new column address. Random Column Address Change operation can be done multiple times within the same page. 31 TC58NVG1S3ETA00 Busy t R M+1 M M+2 ...
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... R DCBSYR1 3 2 31h 0 1 31h 2 3 2111 Page Address N Column 0 Page N Page Page 31h & RE clock 32 TC58NVG1S3ETA00 t t DCBSYR1 DCBSYR1 3Fh 2 3 2111 0 Page Address Page Address Page Page 3Fh & RE clock 31h & RE clock ...
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... RE clock from the start address designated in the address input cycle. (3 cycle) Address input 30 Page Address PA0 to PA16 (District cycle) Address input 05 E0 Column Address CA0 to CA11 (District 0) Address input 05 E0 Column Address CA0 to CA11 (District 1) District 1 Reading Selected page 33 TC58NVG1S3ETA00 Data output (District 0) B Data output (District 1) 2010-05-21C ...
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... CA0 to CA11, PA0 to PA16 CA0 to CA11 (Page m63 ; District 0) Address input Address input 05 Column + Page Address Column Address CA0 to CA11, PA0 to PA16 CA0 to CA11 (Page n63 ; District 1) 34 TC58NVG1S3ETA00 Data output (District 0) E0 Data output (District 1) Return to A Repeat a max of 63 times E0 ...
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... There is no order limitation of the District for the address input. For example, following operation is accepted; (60) [District 0] (60) [District 1] (30) (60) [District 1] (60) [District 0] (30) It requires no mutual address relation between the selected blocks from each District. (c) signal WP Make sure is held to High level when Multi Page Read operation is performed WP TC58NVG1S3ETA00 35 2010-05-21C ...
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... Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Din Din Din 85h Col. M’ Col. M’ Program Reading & verification 36 TC58NVG1S3ETA00 Status 70h Out Din Din Din Din 10h Busy 2010-05-21C 70h ...
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... Block) Block 0 Block 2 Block 2044 Block 2046 tPROG ”0” Address & Data Input 10h 70h I/O0 CA0~CA11 : Valid ”1” PA0~PA5 : Valid Fail PA6 : District1 PA7~PA16 : Valid 10h Plane 1 (1024 Block) Block 1 Block 3 Block 2045 Block 2047 37 TC58NVG1S3ETA00 Pass 2010-05-21C ...
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... Status Output 3 3 Data for Page Data for Page Page the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page) PROG 38 TC58NVG1S3ETA00 t DCBSYW2 15h 70h Add Add Add Add Add 80h Din Din Page ...
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... Page 2 If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2 39 TC58NVG1S3ETA00 pin after the 10h command ...
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... Program with Data input Data Cache command command Address Data input Address 0 to 2111 input input (District 1) (District 0) District 1 40 TC58NVG1S3ETA00 Data input command Dummy Auto Page for multi-page Program Program program command command Address Data input Data input input 0 to 2111 ...
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... Fail: 1 page program operation, it shows “Fail”. Pass: 0 Fail shows the Pass/Fail condition of Pass: 0 Fail: 1 each district. For details on “Chip Status1” and “Chip Status2”, refer to section Ready: 1 Busy: 0 “Status Read”. Ready: 1 Busy: 0 Protect: 0 Not Protect TC58NVG1S3ETA00 2010-05-21C ...
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... Operating restriction during the Multi Page Program with Data Cache operation (Restriction) The operation has to be terminated with “10h” command. Once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for Status Read command and reset command. TC58NVG1S3ETA00 42 2010-05-21C ...
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... After the Ready state, Data for Page output from the Data Cache while the data of Page M is being programmed Address input Data input Address When changing data, CA0 to CA11, PA0 to PA16 changed data is input. (Page M) 3 Data for Page N Data for Page M 43 TC58NVG1S3ETA00 15 00 Address input 3A Data output Address Col = 0 start CA0 to CA11, PA0 to PA16 (Page N+P1 DCBSYW2 ...
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... Col = 0 start CA0 to CA11, PA0 to PA16 (Page N+P2 DCBSYW2 DCBSYR2 7 8 Data for Page Data for Page Page Page TC58NVG1S3ETA00 Address input 00 3A Data output Address Col = 0 start CA0 to CA11, PA0 to PA16 (Page N+Pn DCBSYR2 9 Data for Page Page − 1 Page ...
Page 45
... If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High level when Page Copy (2) operation is performed. Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence 10 70 Status output 11 t (*1) PROG Data for Page TC58NVG1S3ETA00 here will be expected as the following, PROG 2010-05-21C ...
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... Address PA0 to PA16 (Page m1 ; District 0) t DCBSYW2 Address input E0 Data output 00 Address CA0 to CA11 CA0 to CA11, PA0 to PA16 (Col = 0) 46 TC58NVG1S3ETA00 Address input 05 E0 Data output Address CA0 to CA11 (Col = 0) Data input 11 Address t DCBSYW1 Address input 3A Address PA0 to PA16 (Page n1 ; District 1) ...
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... If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High level when Multi Page Copy (2) operation is performed. Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence max. PROG 47 TC58NVG1S3ETA00 15 t DCBSYW2 Address input 05 ...
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... Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h command input, input the FFh reset command to terminate the operation. D0 command Busy D0 Erase Start command District 1 Busy 48 TC58NVG1S3ETA00 Pass 70 I/O Status Read Fail command Pass 71 I/O Status Read ...
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... Description I/O8 I/ level cell 4 level cell 8 level cell 16 level cell 49 TC58NVG1S3ETA00 See See table 5 table 5 I/O4 I/O3 I/O2 I/O1 Hex Data 98h DAh ⎯ ⎯ ⎯ ⎯ See table ⎯ ...
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... Data Page Size (without redundant area) Block Size (without redundant area) 5th Data Plane Number Description I/O8 I/O7 I/ 128 KB 256 KB 512 KB Description I/O8 I/O7 I/O6 1 Plane 2 Plane 4 Plane 8 Plane 50 TC58NVG1S3ETA00 I/O5 I/O4 I/O3 I/O2 I/ I/O5 I/O4 I/O3 I/O2 I/ 2010-05-21C ...
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... The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not 15h or 31h. Page Program Cache Program Block Erase Pass/Fail Pass/Fail Invalid Pass/Fail Ready/Busy Ready/Busy Ready/Busy Ready/Busy Write Protect Write Protect 51 TC58NVG1S3ETA00 Read Cache Read Invalid Invalid Ready/Busy Ready/Busy Write Protect 2010-05-21C ...
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... The response to a “FFh” Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during programming 80 10 Internal Device Device 2 3 Busy 70h Status on Device 1 Status on Device pin signals from multiple devices are wired together as shown in the FF t RST 52 TC58NVG1S3ETA00 Device N 00 (max 10 μ s) 2010-05-21C N 1 Device ...
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... When a Status Read command (70h) is input after a Reset When two or more Reset commands are input in succession The second FF t RST FF (max 6 μ RST (max 6 μ RST 70 ( command is invalid, but the third 53 TC58NVG1S3ETA00 00 (max 500 μ I/O status : Pass/Fail → Pass : Ready/Busy → Ready (2) ( command is valid. 2010-05-21C ...
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... Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of commands while in the Busy state During the Busy state, do not input any command except 70h(71h) and FFh max Operation FF Reset 54 TC58NVG1S3ETA00 Don’t care V IL Don’t care 2010-05-21C ...
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... DATA IN: Data (1) Page 0 Page 1 Page 2 Page 31 Page 63 FF Mode specified by the command. Ex.) Random page program (Prohibition) Data (64) DATA IN: Data (1) Data register (1) (2) (3) Page 31 (32) Page 63 (64) 55 TC58NVG1S3ETA00 10 Programming cannot be executed. Data (64) Data register Page 0 (2) Page 1 (32) Page 2 (3) (1) (64) 2010-05-21C ...
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... Because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary Ready 1.5 μ s 1.0 μ 0.5 μ Ω 56 TC58NVG1S3ETA00 00 [A] 70 Status output Status Read Fail 80 10 Address Data N input buffer consists of an open drain Busy 3 25°C = 100 pF ...
Page 57
... Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns MIN) WW Disable Programming WE DIN (100 ns MIN) WW Enable Erasing WE DIN (100 ns MIN) WW Disable Erasing WE DIN (100 ns MIN TC58NVG1S3ETA00 2010-05-21C ...
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... When six address cycles are input Although the device may read in a sixth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00h Program operation CLE CE WE ALE I/O 80h Address input Ignored Address input 58 TC58NVG1S3ETA00 30h Ignored Data input 2010-05-21C ...
Page 59
... Several programming cycles on the same page (Partial Page Program) Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1 s 4th programming Result Data Pattern 1 All 1 s Data Pattern 2 All 1 s Data Pattern 2 59 TC58NVG1S3ETA00 All 1 s Data Pattern 4 Data Pattern 4 2010-05-21C ...
Page 60
... Read either column 0 or 2048 of the 1st page or the 2nd page of each block. If the data of the column is not Start FF (Hex), define the block as a bad block. Block Fail Read Check Pass Bad Block * 1 Last Block Yes End 60 TC58NVG1S3ETA00 TYP. MAX UNIT ⎯ 2048 Block 2010-05-21C ...
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... Status Read after Program → Block Replacement ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses Block A to Block creating a bad block table or by using another appropriate scheme). Block B 61 TC58NVG1S3ETA00 2010-05-21C ...
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... After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become usable again. Write/Erase Endurance [Cycles] 62 TC58NVG1S3ETA00 2010-05-21C ...
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... Package Dimensions Weight: 0.53g (typ.) TC58NVG1S3ETA00 63 2010-05-21C ...
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... Modified “FEATURES”. Revised “APPLICATION NOTES AND COMMENT” (14). 2010-01-25 1.04 Deleted an invalid description at Page 30. Deleted Confidential notation. Changed “RESTRICTIONS ON PRODUCT USE”. 2010-05-21 1.05 Corrected TIMING DIAGRAM of ID Read. TC58NVG1S3ETA00 64 2010-05-21C ...
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... Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. TC58NVG1S3ETA00 65 2010-05-21C ...