TC58NVG1S3ETA00 Toshiba, TC58NVG1S3ETA00 Datasheet - Page 27

• Manufacturer Part Number: TC58NVG1S3ETA00
• Manufacturer: Toshiba

Specifications of TC58NVG1S3ETA00

• Cell Type: NAND
• Density: 2Gb
• Access Time (max): 30us
• Interface Type: Serial
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The device is a serial access memory which utilizes time-sharing input of address information.
PIN FUNCTIONS
Command Latch Enable: CLE
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable:
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable:
Read Enable:
I/O Port: I/O1 to 8
the device.
Write Protect:
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
in Busy state (
(
pulled-up to Vccq with an appropriate resister.
CE signal is ignored when device is in Busy state (
RY
If
The CLE input signal is used to control loading of the operation mode command into the internal command
The ALE signal is used to control loading address information into the internal address register. Address
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
The WE signal is used to control the acquisition of data from the I/O port.
The RE signal controls serial data output. Data is available t
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
The
/
RY
BY
RY
/
BY
= H) after completion of the operation. The output buffer for this signal is an open drain and has to be
/
BY
signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee.
RY
RY
CE
WE
WP
RE
output signal is used to indicate the operating condition of the device. The
/
BY
/
BY
= L) during the Program, Erase and Read operations and will return to Ready state
RY
27
/
BY
= L), such as during a Program or Erase or Read
REA
after the falling edge of RE .
TC58NVG1S3ETA00
RY
2010-05-21C
/
BY
signal is