TC58NVG1S3ETA00 Toshiba, TC58NVG1S3ETA00 Datasheet - Page 32

• Manufacturer Part Number: TC58NVG1S3ETA00
• Manufacturer: Toshiba

Specifications of TC58NVG1S3ETA00

• Cell Type: NAND
• Density: 2Gb
• Access Time (max): 30us
• Interface Type: Serial
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Cache
Page Buffer
Cell Array
RY
Read Operation with Read Cache
started from the beginning.
CLE
ALE
/
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory
cell to data register) will be reduced.
1
2
3
4
5
6
7
WE
CE
RE
BY
I/O
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max.
After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time
period can be detected by Ready/Busy signal.
Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously.
The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max..
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously
The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for
tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately
after the completion of serial data out.
1
00h
Page N
Col. M
30h
Page N
30h
1
Page N + 1
t
1
2
R
31h
31h & RE clock
Page N
Column 0
2
t
DCBSYR1
0
Page Address N
1
2
3
3
3
Page N
2111
3
32
Page N + 2
31h
4
4
t
31h & RE clock
Page N + 1
DCBSYR1
Page Address N + 1
0
1
2
3
5
2111
5
5
Page N + 1
3Fh
6
6
t
TC58NVG1S3ETA00
DCBSYR1
0
3Fh & RE clock
Page Address N + 2
Page N + 2
1
2
3
2010-05-21C
2111
7
7
Page N + 2