TC58NVG1S3ETA00 Toshiba, TC58NVG1S3ETA00 Datasheet - Page 35

• Manufacturer Part Number: TC58NVG1S3ETA00
• Manufacturer: Toshiba

Specifications of TC58NVG1S3ETA00

• Cell Type: NAND
• Density: 2Gb
• Access Time (max): 30us
• Interface Type: Serial
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Supplier Unconfirmed

(3) Notes
(a) Internal addressing in relation with the Districts
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•
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(b) Address input restriction for the Multi Page Read operation
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c)
Make sure
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
There are following restrictions in using Multi Page Read;
WP
The device consists from 2 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
signal
WP
is held to High level when Multi Page Read operation is performed
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TC58NVG1S3ETA00
2010-05-21C