TC58NVG1S3ETA00 Toshiba, TC58NVG1S3ETA00 Datasheet - Page 38

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TC58NVG1S3ETA00

Manufacturer Part Number
TC58NVG1S3ETA00
Description
Manufacturer
Toshiba
Datasheet

Specifications of TC58NVG1S3ETA00

Cell Type
NAND
Density
2Gb
Access Time (max)
30us
Interface Type
Serial
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
256M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Part Number
Manufacturer
Quantity
Price
Part Number:
TC58NVG1S3ETA00
Manufacturer:
MICROCHIP
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Part Number:
TC58NVG1S3ETA00
Manufacturer:
Toshiba
Quantity:
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RY
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ALE
RE
/
WE
CE
BY
I/O
Data Cache
Page Buffer
Cell Array
Auto Page Program Operation with Data Cache
sequenced has to be started from the beginning.
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
80h
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1
2
3
4
5
6
Add Add Add Add
Data for Page N is input to Data Cache.
Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (t
Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.
By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + 1 (t
Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.
The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
Page N
Page N
1
t
PROG
Data for Page N
= t
Add
PROG
Din
for the last page + t
Din
1
Din
15h
2
Data for Page N
2
PROG
t
70h
DCBSYW2
Status Output
of the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page)
80h
3
Add Add Add Add
Data for Page N + 1
Page N + 1
3
Add
38
Din
Din
Data for Page N + 1
3
4
Page N + 1
Din
15h
4
70h
t
Status Output
DCBSYW2
DCBSYW2
).
5
80h
Data for Page N + P
Page N + P − 1
Add Add Add Add
5
Page N + P
Add
TC58NVG1S3ETA00
Din
Din
5
6
DCBSYW2
Din
2010-05-21C
10h
Page N + P
).
6
Status Output
70h
t
PROG (NOTE)

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