GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 110

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
12.4.2
12.4.2.1
102
Figure 30. Output Timing Measurement Conditions
Figure 31. Input Timing Measurement Conditions
Timing Parameters
Measurement and Test Conditions
Figure
done. The component test guarantees that all timings are met with minimum clock slew rate
(slowest edge) and voltage swing. The design must guarantee that minimum timings are also met
with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must
guarantee proper input operation for input voltage swings and slew rates that exceed the specified
test conditions.
INPUT
Table 39. Measure and Test Condition Parameters
OUTPUT
OUTPUT
CLK
30,
Tri-State
DELAY
Figure
CLK
31, and
Symbol
V_th
V_tl
V
V
th
tl
Table 39
V_test
V_test
define the conditions under which timing measurements are
V_test
PCI Level
0.6V
0.2V
T_on
CC
CC
T_su
V_step
T_off
T_val
inputs
valid
V_test
CardBus Level
T_h
V_test
0.6V
0.2V
CC
CC
V_test
Units
V
V
V_max
V_th
V_tl
V_th
V_tl
Notes
Datasheet