GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 26

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
18
Figure 3. Control/Status Register I/O Write Cycle
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82559 controls
the TRDY# signal and provides valid data on each data access. The 82559 allows the CPU to issue
only one read cycle when it accesses the Control/Status Registers, generating a disconnect by
asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not
ready.
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the
82559 with valid data on each data access immediately after asserting IRDY#. The 82559 controls
the TRDY# signal and asserts it from the data access. The 82559 allows the CPU to issue only one
I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP#
signal. This is true for both memory mapped and I/O mapped accesses.
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
1
I/O WR
ADDR
2
3
DATA
BE#
4
5
6
7
8
9
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