GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 86

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
9.1.14.3
78
Table 20. LAN Function Event Mask Register
Table 21. LAN Function Present State Register
LAN Function Present State Register
The Function Present State register reflects the current state of the LAN function that may cause a
status change or interrupt.
4
3
2
1
0
31:16
15
14:5
4
3
2
1
0
Bits
Bits
GWAKE
Reserved
BVD RDY
BVD WP
Reserved
Reserved
INTR
Reserved
GWAKE
Reserved
BVD RDY
BVD WP
Reserved
Function
Function
0b
0
0b
0b
0b
0b
0b
0
0
0
0b
0b
0b
Default
Default
This bit is the general wake-up mask. When this bit equals 0b, it masks
the Ethernet function wake-up events towards the CSTSCHG signal. It
has no effect on the LAN Function Event register. The 82559 can
assert the CSTSCHG signal in the following configuration of masked
bits: wake-up bit AND general wake-up bit, or PME Enable bit in the
PMCSR register only.
Bit 3 is reserved in the CardBus Specification.
Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
Bit 1 is used as the BVD Write Protect (WP) bit.
Bit 0 is reserved in the CardBus Specification.
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. It reflects the current state of the
Ethernet source of the interrupt regardless of the mask value. It is set
when the Ethernet function has a pending interrupt and cleared when
the software driver acknowledges all active interrupts through the SCB
Command Word.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It reflects the current state of the
Ethernet source of CSTSCHG. It is a logical OR result of the gated
three most significant bits in the PMDR: Link Status Change, Magic
Packet, and Interesting Packet. The Link Status change bit is gated by
the Link Status Change Wake Enable bit in the Configuration
command. The Magic Packet bit is gated by the Magic Packet Wake-up
disable bit in the Configuration command. The Interesting Packet bit is
gated by the programmable filter command.
Bit 3 is reserved in the CardBus Specification.
Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
Bit 1 is used as the BVD Write Protect (WP) bit.
Bit 0 is reserved in the CardBus Specification.
Description
Description
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