GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 69

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

8.1.10
8.1.11
8.1.12
Datasheet
Table 6. Base Address Register Functionalities
LAN/modem combination design, the CFCS# signal will be de-asserted (high) when the Boot
Disable bit is not set in the EEPROM and the ROM enable bit is set in the Expansion ROM Base
Address Register. After the initial access to the Expansion ROM BAR, the Boot Disable bit is
cleared and CFCS# is asserted (low) enabling the modem to use the local bus.
Base Address Registry Summary
The preceding description of the Base Address Registers’ functions are summarized in the
following table:
a. The Expansion BAR can be disabled by setting the Boot Disable bit in the EEPROM.
CardBus Card Information Structure (CIS) Pointer
The Card Information Structure (CIS) pointer is a Dword hard coded read only register. It is
meaningful only in a CardBus system (in a PCI system it is zero). The CIS pointer defines where
the CIS structure is mapped in the Flash address space.
PCI Subsystem Vendor ID and Subsystem ID Registers
The Subsystem Vendor ID field identifies the vendor of an 82559-based solution. The Subsystem
Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special
Interest Group (SIG).
The Subsystem ID field identifies the 82559-based specific solution implemented by the vendor
indicated in the Subsystem Vendor ID field.
The 82559 provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After
hardware reset is de-asserted, the 82559 automatically reads addresses AH through CH of the
EEPROM. The first of these 16-bit values is used for controlling various 82559 functions. The
second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the
default values for the Subsystem ID and Subsystem Vendor ID are 0H and 0H, respectively.
Expansion
Register
Name
BAR0
BAR1
BAR2
BAR
a
31:4
3:0
PCI Function
Memory CSR
Bits
BootROM
I/O CSR
Flash
R
R
R/W
1000H
3H
Default
PCI Window
128 Kbyte
1 Mbyte
4 Kbyte
4 Kbyte
Ethernet CIS Pointer (above the physical Flash window)
CIS in the Flash window
CIS at offset + 64 Kbyte
(Disabled by EEPROM)
CardBus Function
Memory CSR
I/O CSR
N/A
Networking Silicon — 82559
Description
CardBus Window
128 Kbyte
1 Mbyte
4 Kbyte
4 Kbyte
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