GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 24

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
4.1.2
4.2
4.2.1
4.2.1.1
16
Initialization Effects on TCO Functionality
The 82559 has the ability to be controlled by two masters, the host CPU on the PCI bus and the
TCO controller on the SMB. The 82559 may be initialized by the PCI bus during SMB operation.
The table below summarizes the effect of those sources:
a. ISOLATE# acts as reset on its trailing edge. While the 82559 is in the D3 power state, the PCI RST# initializes the 82559
b. SMB commands in process will be terminated immediately.
PCI and CardBus Interface
82559 Bus Operations
After configuration, the 82559 is ready for its normal operation. As a Fast Ethernet Controller, the
role of the 82559 is to access transmitted data or deposit received data. In both cases the 82559, as
a bus master device, will initiate memory cycles via the PCI bus to fetch or deposit the required
data.
In order to perform these actions, the 82559 is controlled and examined by the CPU via its control
and status structures and registers. Some of these control and status structures reside in the 82559
and some reside in system memory. For access to the 82559’s Control/Status Registers (CSR), the
82559 acts as a slave (in other words, a target device). The 82559 serves as a slave also while the
CPU accesses its 128 Kbyte Flash buffer or its EEPROM. When the 82559 is in modem mode, it
also acts as a slave. Details regarding modem interface are described in
Flash/Modem Interface” on page
Section 4.2.1.1, “82559 Bus Slave Operation”
by a description of the 82559 operation as a bus master (initiator) in
Master Operation” on page
82559 Bus Slave Operation
The 82559 serves as a target device in one of the following cases:
ALTRST#, PCI RST#, or
ISOLATE#
D3 to D0 transition
Software Reset,
Selective Reset, or D3 to
D0 transition
•
Initialization Source
on the trailing edge.
CPU accesses to the 82559 System Control Block (SCB) Control/Status Registers (CSR)
a
The SMB is terminated instantaneously.
The SMB cycle is aborted. During SMB read
commands, the 82559 transfers zeros until the end of
the cycle. An SMB write cycle has no effect on the
82559. The 82559 asserts the SMBALRT# after a D3
to D0 transition. The 82559 indicates its initialization
status to the TCO controller via an active initialization
bit in the Status word.
The SMB cycle is aborted. During SMB read
commands, the 82559 transfers zeros until the end of
the cycle. An SMB write cycle has no affect on the
82559. After a software reset, the 82559 reports its
initialization in the same manner as in a D3 to D0
transition.
22.
33.
SMB Behavior
describes the 82559 slave operation. It is followed
b
Section 4.2.1.2, “82559 Bus
Section 4.6, “Parallel
Initialized to inactive
Initialized to inactive
Unaffected
Status and Receive
Enable
Datasheet