GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 25

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Figure 2. Control/Status Register I/O Read Cycle
The CSR and the 1 Mbyte Flash buffer are considered by the 82559 as two totally separated
memory spaces. The 82559 provides separate Base Address Registers (BARs) in the configuration
space to distinguish between them. The size of the CSR memory space is 4 Kbyte in the memory
space and 64 bytes in the I/O space. The 82559 treats accesses to these memory spaces differently.
4.2.1.1.1 Control/Status Register (CSR) Accesses
The 82559 supports zero wait state single cycle memory or I/O mapped accesses to its CSR space.
Separate BARs request 4 Kbytes of memory space and 64 bytes of I/O space to accomplish this.
Based on its needs, the software driver will use either memory or I/O mapping to access these
registers. The 82559 provides 4 valid Kbytes of CSR space, which include the following elements:
The figures below show CSR zero wait state I/O read and write cycles. In the case of accessing the
Control/Status Registers, the CPU is the initiator and the 82559 is the target of the transaction.
•
•
•
•
•
•
•
•
•
•
•
•
CPU accesses to the EEPROM through its CSR
CPU accesses to the 82559 PORT address via the CSR
CPU accesses to the MDI control register in the CSR
CPU accesses to the Flash control register in the CSR
CPU accesses to the 128 Kbyte Flash
System Control Block (SCB) registers
PORT register
Flash control register
EEPROM control register
MDI control register
Flow control registers
CardBus registers
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
1
I/O RD
ADDR
2
3
BE#
DATA
4
5
Networking Silicon — 82559
6
7
8
9
17