GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 42

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
34
Figure 11. 64-word EEPROM Read Instruction Waveform
All accesses, either read or write, are preceded by a command instruction to the device. The address
field is six bits for a 64 register EEPROM or eight bits for a 256 register EEPROM. The end of the
address field is indicated by a dummy zero bit from the EEPROM, which indicates the entire
address field has been transferred to the device. An EEPROM read instruction waveform is shown
in the figure below.
The 82559 may also use the EEPROM for heartbeat packet transmission (systems without a TCO
controller are also supported). In these designs, the EEPROM is accessed through time windows
autonomously by the 82559 hardware. During these time windows, the 82559 will respond with a
PCI Retry to both EEPROM and Flash accesses.
The 82559 performs an automatic read of five words (0H, 1H, 2H, AH, and DH) of the EEPROM
after the de-assertion of Reset. It may read six more words (BH, CH, FBH, FCH, FDH, and FEH) if
the modem bit is set in the EEPROM (word AH, bit 0).
EEDO
EESK
EECS
EEDI
READ OP code
A
5
A
4
A
3
A
2
A
A
A
1
1
0
A
0
D
15
D
0
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