GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 64

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
8.1.2
56
Figure 22. PCI Command Register
Table 4.
PCI Command Register
The 82559 Command register at word address 04H in the PCI configuration space provides control
over the 82559’s ability to generate and respond to PCI cycles
82559 is logically disconnected from the PCI bus for all accesses except configuration accesses
The format of this register is shown in the figure below.
Note that bits three, five, seven, and nine are set to 0b. The table below describes the bits of the PCI
Command register.
PCI Command Register Bits
15:10
8
6
4
2
1
0
Bits
SERR# Enable
Parity Error Response
Memory Write and Invalidate Enable
Bus Master Enable
Reserved
SERR# Enable
Parity Error Control
Memory Write and
Invalidate Enable
Bus Master
Memory Space
I/O Space
Name
15
Reserved
This bit controls a device’s ability to enable the SERR# driver. A value of 0b
disables the SERR# driver. A value of 1b enables the SERR# driver. This
bit must be set to report address parity errors. In the 82559, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to parity errors. A value of 0b causes
the device to ignore any parity errors that it detects and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82559, this bit is configurable and has a default value of 0b.
This bit controls a device’s ability to use the Memory Write and Invalidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write and Invalidate command. In the 82559, this bit is
configurable and has a default value of 0b.
This bit controls a device’s ability to act as a master on the PCI bus. A value
of 0b disables the device from generating PCI accesses. A value of 1b
allows the device to behave as a bus master. In the 82559, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to the memory space accesses. A
value of 0b disables the device response. A value of 1b allows the device to
respond to memory space accesses. In the 82559, this bit is configurable
and its default value of 0b.
This bit controls a device’s response to the I/O space accesses
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82559, this bit is configurable and
the default value of 0b.
These bits are reserved and should be set to 000000b.
10
0
9
8
Description
0
7
.
If a 0His written to this register, the
6
0
5
4
0
3
2
.
Datasheet
1
A value of
0
.