GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 85

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.1.14.1
9.1.14.2
Datasheet
Table 19. LAN Function Event Register
Table 20. LAN Function Event Mask Register
Note: Access to the CSTSCHG registers in PCI mode is forbidden.
The 82559 supports only the interrupt and general wake-up event bits in the card status change
registers. These registers compliment the PCI Power Management registers in a non-ACPI
compliant OS. They are initialized by a power-up reset on the ALTRST# pin.
The location of these registers should be specified within the configuration space pointing to offset
address 30H of the CSR.
LAN Function Event Register
The Function Event register specified the event that changed the status.
LAN Function Event Mask Register
The Function Event Mask register masks CSTSCHG and INTA# assertion.
31:16
15
14:5
4
3
2
1
0
31:16
15
14
13:7
6:5
Bits
Bits
Reserved
INTR
Reserved
GWAKE
Reserved
BVD RDY
BVD WP
Reserved
Reserved
INTR
WKUP
Reserved
PWM
BAM
Function
Function
0
0b
0
0b
0b
0b
0b
0b
0
0b
0b
0
0
Default
Default
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for as the interrupt bit. It is set when the Ethernet
interrupt source is set, regardless of the mask value. It is cleared when
the OS writes 1b to this field and the interrupt source has been
serviced. Writing 0b to this field has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It is set when the Ethernet wake-
up source is set, regardless of the mask value. Writing 1b to this field
clears this bit and the PME Status bit in the PMCSR. Writing 0b to this
field has no effect. Note that writing 1b to the PME Status bit in the
PMCSR has the same effect.
Bit 3 is reserved in the CardBus Specification.
Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
Bit 1 is used as the BVD Write Protect (WP) bit.
Bit 0 is reserved in the CardBus Specification.
Bits [31:16] are reserved in the CardBus Specification.
This bit is the interrupt mask. When this bit equals 0b, it masks the
Ethernet function INTA# line but has no effect on the LAN Function
Event register. The Ethernet function can assert the INTA# signal only
when both fields are enabled: the interrupt bit and the “M” bit in the
System Control Block (SCB) register within the CSR space. The
interrupt mask bit affects the INTA# masking.
This bit is the wake-up mask. When this bit equals 0b, it masks the
Ethernet function CSTSCHG signal but has no effect on the LAN
Function Event register. This bit is dependent on bit 4 of this register.
Bits [13:7] are reserved in the CardBus Specification.
These bits are used for Pulse Width Modulation Binary Audio Enable
(PWM BAM).
Description
Description
Networking Silicon — 82559
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