GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 79

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.0
9.1
Datasheet
Figure 28. 82559 Control/Status Register
Control/Status Registers
LAN (Ethernet) Control/Status Registers
The 82559’s Control/Status Register (CSR) is illustrated in the figure below.
NOTE: In
SCB Status Word:
SCB Command Word:
SCB General Pointer:
PORT Interface:
Flash Control Register:
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
D31
PMDR
the Power Management Driver Register.
EEPROM Control Register
Figure 28
SCB Command Word
Upper Word
Reserved
above, SCB is defined as the System Control Block of the 82559, and PMDR is defined as
Management Data Interface (MDI) Control Register
Receive Direct Memory Access Byte Count
System Control Block General Pointer
Function Present State Register
Function Event Mask Register
The 82559 places the status of its Command and Receive units and
interrupt indications in this register for the CPU to read.
The CPU places commands for the Command and Receive units in
this register. Interrupts are also acknowledged in this register.
The SCB General Pointer register points to various data structures
in main memory depending on the current SCB Command word.
The PORT interface allows the CPU to reset the 82559, force the
82559 to dump information to main memory, or perform an internal
self test.
The Flash Control register allows the CPU to enable writes to an
external Flash.
an external EEPROM.
Flow Control Register
Function Event Register
Force Event Register
D16
Reserved
Reserved
Reserved
Reserved
PORT
General Status
D15
Flash Control Register
SCB Status Word
Lower Word
Networking Silicon — 82559
Early Receive Int
General Control
D0
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
Offset
71