GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 66

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
8.1.4
8.1.5
8.1.6
58
Table 5.
PCI Status Register Bits
PCI Revision ID Register
The Revision ID is an 8-bit read only register with a default value of 08H for the 82559 B-step and
09H for the 82559 C-step. The three least significant bits of the Revision ID can be overridden by
the ID and Revision ID fields in the EEPROM
PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82559 as a network controller, 2H.
The middle byte is a subclass code and specifies the 82559 as an Ethernet controller, 0H. The lower
byte identifies a specific register level programming interface and the 82559 always returns a 0H in
this field.
PCI Cache Line Size Register
In order for the 82559 to support the Memory Write and Invalidate (MWI) command, the 82559
must also support the Cache Line Size (CLS) register in PCI Configuration space. The register
supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is written to
the register is ignored and the 82559 does not use the MWI command. If a value other than 8 or 16
is written into the CLS register, the 82559 returns all zeroes when the CLS register is read. The
figure below illustrates the format of this register.
24
23
20
19:16
Bits
Figure 24. Cache Line Size Register
Parity Error Detected
Fast Back-to-Back
Capabilities List
Reserved
Name
7
0
6
0
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
3. The Parity Error Response bit in the command register (bit 6) is set.
In the 82559, the initial value of the Parity Error Detected bit is 0b. This bit
is set until cleared by writing a 1b.
This bit indicates a device’s ability to accept fast back-to-back transactions
when the transactions are not to the same agent. A value of 0b disables
fast back-to-back ability. A value of 1b enables fast back-to-back ability. In
the 82559, this bit is read only and is set to 1b.
This bit indicates whether the 82559 implements a list of new capabilities
such as PCI Power Management. A value of 0b means that this function
does not implement the Capabilities List. If this bit is set to 1b, the Cap_Ptr
register provides an offset into the 82559 PCI Configuration space pointing
to the location of the first item in the Capabilities List. This bit is set only if
the power management bit in the EEPROM is set.
These bits are reserved and should be set to 0000b.
which the error occurred.
5
0
RW
4
(Section 4.7, “Serial EEPROM
RW
3
Description
2
0
1
0
Interface”).
0
0
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