DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 109

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Table 10-31. Pseudo-Random Pattern Generation
PATTERN TYPE
2
2
(2047 type)
2
2
2
2
Table 10-32. Repetitive Pattern Generation
PATTERN TYPE
all 1s
all 0s
alternating 1s and 0s
double alternating and 0s
3 in 24
1 in 16
1 in 8
1 in 4
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BERT.CR.TNPL and BERT.CR.RNPL
Monitoring the BERT requires reading the
Out of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will
be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it
receives a minimum 6 bit errors within a 64 bit window. The Receive BERT Bit Count Register (BERT.RBCR1) and
the Receive BERT Bit Error Count Register (BERT.RBECR1) will be updated upon the reception of a Performance
Monitor Update signal (e.g. BERT.CR.LPMU). This signal will update the registers with the values of the counter
since the last update and will reset the counters. Please see section
10.11.4 Receive Pattern Detection
Since the Receive BERT is always enabled, it can be used as an off-line monitor. The Receive BERT receives
only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is
enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all
zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits
1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection performs either PRBS
synchronization or repetitive pattern synchronization.
10.11.4.1 Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
9
11
15
20
20
23
-1 O.153 (511 type)
-1 O.152 and O.153
-1 O.151
-1 O.153
-1 O.151 QRSS
-1 O.151
PTF[4:0]
(hex)
0D
04
08
10
02
11
PTF[4:0]
(hex)
BERT.PCR Register
NA
NA
NA
NA
NA
NA
NA
NA
PLF[4:0]
BERT.PCR Register
(hex)
BERT.SR
0A
0E
08
13
13
16
PLF[4:0]
(hex)
0F
00
00
01
03
17
07
03
109 of 230
Register which contains the Bit Error Count (BEC) bit and the
PTS
0
0
0
0
0
0
PTS
1
1
1
1
1
1
1
1
QRSS
0
0
0
0
1
0
QRSS
0
0
0
0
0
0
0
0
10.4.5
0x0D0E
0x080A
0x0408
0x1013
0x0253
0x1116
BERT.
PCR
DS3170 DS3/E3 Single-Chip Transceiver
0x002F
0x0020
0x0020
0x0021
0x0023
0x0037
0x0027
0x0023
BERT.
for more details of the PMU.
PCR
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF20
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR1
0xFFFC
0xFFFF
0xFFFE
0xFFFE
0xFFF1
0xFF01
0x0022
0x0001
BERT.
SPR1
n
+ x
BERT.CR
y
TPIC,
RPIC
+ 1), the
0
0
1
0
0
1