DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 113

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

waveforms onto 75Ω coaxial cable. Refer to
LIU. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or be
disabled. The DS3/E3 LIU conforms to the telecommunications standards listed in
external components required for proper operation.
Figure 10-31. DS3/E3 LIU Block Diagram
10.12.4 Transmitter
10.12.4.1 Transmit Clock
The clock used in the LIU Transmitter is typically based on either the CLAD clock or TCLKI, selected by the
CLADC bit in PORT.CR3.
10.12.4.2 Waveshaping, Line Build-Out, Line Driver
The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI
signal with the waveshape required for interfacing to DS3/E3 lines.
16-11
Because DS3 signals must meet the waveform templates at the cross-connect through any cable length from 0 to
450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater, the TLBO
configuration bit (PORT.CR2.TLBO) should be low. When TLBO is low, output pulses are driven onto the coaxial
cable without any preattenuation. For cable lengths less than 225ft, TLBO should be high to enable the LBO
circuitry. When TLBO is high, pulses are preattenuated by the LBO circuitry before being driven onto the coaxial
cable. The LBO circuitry provides attenuation that mimics the attenuation of 225ft of coaxial cable.
The transmitter line driver can be disabled and the TXP and TXN outputs tri-stated by asserting the LTS
configuration bit (PORT.CR2.LTS). Powering down the transmitter through the TPD configuration bit (CPU bus
mode) also tri-states the TXP and TXN outputs.
FROM DS3/E3
TO DS3/E3 LINE
LINE
(AC Timing Section) show the waveform template specifications and test parameters.
TXPn
TXNn
RXPn
RXNn
VDD
VSS
Supply
Power
Analog
Local
Loopback
Monitor
Driver
Automatic
Equalizer
Adaptive
Control
Clock Rate
Gain
REFCLK
Adapter
+
ALOS
squelch
Recovery
Clock &
Data
Figure 10-31
113 of 230
for a detailed functional block diagram of the DS3/E3
Table 16-7
DS3170 DS3/E3 Single-Chip Transceiver
TO B3ZS/HDB3
FROM B3ZS/HDB3
DECODER
ENCODER
Table
through
5-1.
Table 16-9
Figure 2-1
and
shows the
Figure