DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 127

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error if the port is configured for global error
insertion. An error(s) is inserted at the next opportunity when this bit transitions from low to high. The
GL.CR1.MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (GL.SR.PMS) goes high, then it
should be brought back low which clears the PMS status bit.
Bit 2: Latched Status Bit Clear on Read Enable (LSBCRE). This signal determines when latched status register
bits are cleared.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers to their
default state. This bit must be set high for a minimum of 100ns. See the
Note: The default state is a 1 (after a general reset, this bit will be set to one).
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit), will be reset to their default state. This bit must be set high for a minimum of 100ns. See the
Power-Down
0 = Pin is high impedance when not active
1 = Pin drives high when not active
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
0 = Normal operation
1 = Force all data path registers to their default values
0 = Normal operation
1 = Force all internal registers to their default values
section 10.3.
TMEI
15
--
0
7
0
MEIMS
INTM
14
0
6
0
GL.CR1
Global Control Register 1
002h
GPM1
13
--
0
5
0
127 of 230
GPM0
12
--
0
4
0
--
PMU
11
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
Reset and Power-Down
LSBCRE
10
--
0
2
0
RSTDP
--
9
0
1
1
section 10.3.
Reset and
RST
--
8
0
0
0