DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 144

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

12.4 BERT
12.4.1 BERT Register Map
The BERT utilizes twelve registers.
Table 12-13. BERT Register Map
12.4.2 BERT Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Performance Monitoring Update Mode (PMUM) – When 0, a performance monitoring update is initiated by
the LPMU register bit. When 1, a performance monitoring update is initiated by the global or port PMU register bit.
Note: If the LPMU bit or the global or port PMU bit is one, changing the state of this bit may cause a performance
monitoring update to occur.
Bit 6: Local Performance Monitoring Update (LPMU) – This bit causes a performance monitoring update to be
initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance
monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance
monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit
goes high; an update might not be performed. This bit has no affect when PMUM=1.
Bit 5: Receive New Pattern Load (RNPL) – A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit
Address
06Ah
06Ch
06Eh
07Ah
07Ch
07Eh
060h
062h
064h
066h
068h
070h
072h
074h
076h
078h
PMUM
15
BERT.CR
BERT.PCR
BERT.SPR1
BERT.SPR2
BERT.TEICR
--
BERT.SR
BERT.SRL
BERT.SRIE
--
BERT.RBECR1
BERT.RBECR2
BERT.RBCR1
BERT.RBCR2
--
--
--
0
7
0
Register
LPMU
14
--
0
6
0
BERT.CR
BERT Control Register
060h
BERT Control Register
BERT Pattern Configuration Register
BERT Seed/Pattern Register #1
BERT Seed/Pattern Register #2
BERT Transmit Error Insertion Control Register
Unused
BERT Status Register
BERT Status Register Latched
BERT Status Register Interrupt Enable
Unused
BERT Receive Bit Error Count Register #1
BERT Receive Bit Error Count Register #2
BERT Receive Bit Count Register #1
BERT Receive Bit Count Register #2
Unused
Unused
Register Description
RNPL
13
--
0
5
0
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RPIC
12
--
0
4
0
MPR
11
--
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
APRD
10
--
0
2
0
TNPL
--
9
0
1
0
TPIC
--
8
0
0
0