DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 64

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

reset values. The processor bus output signals are also forced to be HIZ when the RST pin is active (low). The
global reset bit (GL.CR1.RST) stays set after a one is written to it, but is reset to zero when the external RST pin is
active or when a zero is written to it.
At the port level, the global reset signal combines with the port reset bit in the port control register
(PORT.CR1.RST) to create a port reset signal. The port reset signal resets all the status and control registers on
the port to their default values and resets all the other flops, except PORT.CR1.RST, to their reset values. The port
reset bit (PORT.CR1.RST) stays set after a one is written to it, but is reset to zero when the global reset signal is
active or when a zero is written to it.
The data path reset function is a little different from the “general” reset function. The data path reset signal does not
reset the control register bits, but it does reset all of the status registers, counters and flops, the “general” reset
signal resets everything including the control register bits, excluding the reset bit. All clocks are functional, being
controlled by configuration bits, while data path reset is active. The LIU and CLAD circuits will be operating
normally during data path reset which allows the internal phase locked loops to settle as quickly as possible. The
LIU will be sending all zeroes (LOS) since data path reset will be forcing the transmit TPOS and TNEG to logic
zero. (NOTE: The BERT data path does not get reset when PORT.CR1.RSTDP is active.)
The global data path reset bit (GL.CR1.RSTDP) gets set to one when the global reset signal is active. The port
data path reset bit (PORT.CR1.RSTDP) and the port power-down bit (PORT.CR1.PD) bit gets set to one when the
port reset signal is active. These control bits will be cleared when a zero is written to them when the port reset
signal is not active. The global data path reset signal is active when the global data path reset bit is set. The port
data path reset signal is active when either the global data path reset bit or the port data path reset bit is set. The
port power-down signal is active when the port power-down bit is set.
Figure 10-5. Reset Sources
NOTE: Assumes
active high signals
RST pin
D
D
CLR
CLR
SET
SET
Q
Q
Q
Q
GL.CR1. RSTDP
GL.CR1. RST
64 of 230
PORT.CR1.
RSTDP
D
D
D
PORT.CR1. PD
CLR
CLR
CLR
SET
SET
SET
Q
Q
Q
Q
Q
Q
PORT.CR1.
RST
DS3170 DS3/E3 Single-Chip Transceiver
Port Data Path Reset
Global Reset
Port Reset
Global Data Path Reset
Port Power Down