SC68C2550BIB48,151 NXP Semiconductors, SC68C2550BIB48,151 Datasheet
SC68C2550BIB48,151
Specifications of SC68C2550BIB48,151
935278765151
SC68C2550BIB48-S
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SC68C2550BIB48,151 Summary of contents
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SC68C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode P interface Rev. 03 — 9 October 2009 1. General description The SC68C2550B is a two channel Universal Asynchronous Receiver and ...
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... NXP Semiconductors I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic capabilities: N Loopback controls for communications link fault isolation I Prioritized interrupt system controls I Modem control functions (CTS, RTS, DSR, DTR, RI, CD) 3 ...
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... NXP Semiconductors 4. Block diagram SC68C2550B DATA BUS R/W CONTROL RESET REGISTER SELECT CS IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC68C2550B SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs AND LOGIC LOGIC ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Pin description Symbol Pin Type Description Address 0 select bit. Internal register address selection Address 1 select bit. Internal register address selection Address 2 select bit. Internal register address selection Address used to select Channel A or Channel B. A logic LOW selects Channel A, and a logic HIGH selects Channel B ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type Description D0 44 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU the least significant bit and the first data bit ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type Description RXRDYA 31 O Receive Ready A, B (active LOW). These outputs provide the receive FIFO/RHR status for individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1 RXRDYB 18 O transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to read/upload, that is, receive ready status with one or more receive characters available in the FIFO/RHR ...
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... NXP Semiconductors 6. Functional description The SC68C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors 6.2 Internal registers The SC68C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control ...
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... NXP Semiconductors 6.4 Hardware/software and time-out interrupts The interrupts are enabled by IER[3:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC68C2550B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only ...
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... NXP Semiconductors Fig 3. Table 6. Output baud rate 50 75 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.6 DMA operation The SC68C2550B FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s) ...
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... NXP Semiconductors 6.7 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure In the Loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn) are disconnected from their associated interface pins, and instead are connected together internally ...
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... NXP Semiconductors SC68C2550B DATA BUS AND R/W CONTROL RESET LOGIC REGISTER SELECT CS LOGIC IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 4. Internal Loopback mode diagram SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 7. Register descriptions Table 7 assigned bit functions are more fully defined in Table 7. SC68C2550B internal registers Register Default [2] General register set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [3] Special register set DLL DLM XX [1] The value shown in represents the register’s initialized hexadecimal value n/a. ...
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... NXP Semiconductors prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After 7 should be shifted to the center of the start bit. At this time the start bit is sampled, and still a logic validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character ...
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... NXP Semiconductors 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level ...
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... NXP Semiconductors programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDYn pin packages transitions LOW when the FIFO reaches the trigger level, and transitions HIGH when the FIFO empties. 7.3.2 FIFO mode Table 9. ...
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... NXP Semiconductors Table 9. Bit 0 Table 10. FCR[ 7.4 Interrupt Status Register (ISR) The SC68C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 13. Bit 7 6 5:3 2 1:0 Table 14 ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 17. Bit 7 SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Modem Control Register bits description Symbol ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC68C2550B and the CPU. Table 18. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC68C2550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC68C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC68C2550B external reset condition Table 20. Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 21. Output TXA, TXB OP2A, OP2B RTSA, RTSB ...
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... NXP Semiconductors 9. Static characteristics Table 23. Static characteristics +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input voltage IL(clk) V clock HIGH-level input voltage IH(clk) V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage OH I LOW-level input leakage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 24. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t R/W to chip select d1 t read cycle delay d2 t delay from CS to data d3 t data disable time d4 t write cycle delay d6 t delay from write to output d7 t delay to set interrupt from modem ...
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... NXP Semiconductors 10.1 Timing diagrams su1 R Fig 5. General read timing su1 R Fig 6. General write timing SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs valid address w(CS valid data valid address w(CS su2 valid data Rev. 03 — ...
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... NXP Semiconductors (1) CS (write) RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB IRQ (2) CS (read) RIA, RIB (1) CS timing during a write cycle. See (2) CS timing during a read cycle. See Fig 7. Modem input/output timing external clock -------------- - XTAL t w clk Fig 8 ...
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... NXP Semiconductors RXA, RXB IRQ CS (read) Fig 9. Receive timing RXA, RXB RXRDYA, RXRDYB CS (read) Fig 10. Receive ready timing in non-FIFO mode SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Start bit data bits ( data bits ...
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... NXP Semiconductors RXA, RXB RXRDYA, RXRDYB CS (read) Fig 11. Receive ready timing in FIFO mode TXA, TXB IRQ active CS (write) Fig 12. Transmit timing SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Start bit data bits ( Start ...
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... NXP Semiconductors TXA, TXB active CS (write byte #1 TXRDYA, TXRDYB Fig 13. Transmit ready timing in non-FIFO mode TXA, TXB CS (write) active byte #16 TXRDYA, TXRDYB Fig 14. Transmit ready timing in FIFO mode SC68C2550B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 27. Acronym CPU DMA FIFO ISDN LSB MSB TTL UART SC68C2550B_3 Product data sheet ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Data sheet descriptive title changed from “... Motorola P interface” to “... 68 mode P interface” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 7 6.2 Internal registers 6.3 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 Hardware/software and time-out interrupts 6.5 Programmable baud rate generator . . . . . . . . . 9 6 ...