SC68C2550BIB48,151 NXP Semiconductors, SC68C2550BIB48,151 Datasheet - Page 22

IC UART DUAL W/FIFO 48-LQFP

SC68C2550BIB48,151

Manufacturer Part Number
SC68C2550BIB48,151
Description
IC UART DUAL W/FIFO 48-LQFP
Manufacturer
NXP Semiconductors
Type
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s with 16-byte FIFOsr
Datasheet

Specifications of SC68C2550BIB48,151

Number Of Channels
2, DUART
Package / Case
48-LQFP
Features
False-start Bit Detection
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
4.5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3296
935278765151
SC68C2550BIB48-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC68C2550BIB48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
8. Limiting values
SC68C2550B_3
Product data sheet
7.10 SC68C2550B external reset condition
7.9 Scratchpad Register (SPR)
The SC68C2550B provides a temporary data register to store 8 bits of user information.
Table 20.
Table 21.
Table 22.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Register
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
Output
TXA, TXB
OP2A, OP2B
RTSA, RTSB
DTRA, DTRB
IRQ
Symbol
V
V
T
T
P
amb
stg
CC
n
tot
/pack
Parameter
supply voltage
voltage on any other pin
ambient temperature
storage temperature
total power dissipation
per package
Reset state for registers
Reset state for outputs
Limiting values
Reset state
IER[7:0] = 0
FCR[7:0] = 0
ISR[7:1] = 0; ISR[0] = 1
LCR[7:0] = 0
MCR[7:0] = 0
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR[7:4] = input signals; MSR[3:0] = 0
SFR[7:0] = 1
DLL[7:0] = X
DLM[7:0] = X
Reset state
logic 1
logic 1
logic 1
logic 1
3-state condition
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 03 — 9 October 2009
Conditions
at D7 to D0
at any input only pin
operating
Min
-
GND
GND
-
40
65
SC68C2550B
0.3
0.3
© NXP B.V. 2009. All rights reserved.
Max
7
V
5.3
+85
+150
500
CC
+ 0.3
Unit
V
V
V
mW
22 of 36
C
C

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