SC68C2550BIB48,151 NXP Semiconductors, SC68C2550BIB48,151 Datasheet - Page 17

• Manufacturer Part Number: SC68C2550BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s with 16-byte FIFOsr

Specifications of SC68C2550BIB48,151

• Number Of Channels: 2, DUART
• Package / Case: 48-LQFP
• Features: False-start Bit Detection
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3296; 935278765151; SC68C2550BIB48-S

NXP Semiconductors
SC68C2550B_3
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 9.
Table 10.
The SC68C2550B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. A lower level interrupt may be seen after servicing the
higher level interrupt and re-reading the interrupt status bits.
values (bit 0 to bit 3) for the four prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 11.
Table 12.
Bit
0
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
Bit
7:6
5:4
3:1
0
Symbol
FCR[0]
ISR[3]
0
0
1
0
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
FIFO Control Register bits description
RCVR trigger levels
Interrupt source
Interrupt Status Register bits description
FCR[6]
0
1
0
1
Description
FIFOs enabled
ISR[2]
1
1
1
0
0
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
logic 0 = disable the transmit and receive FIFO (normal default condition).
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’ when
other FCR bits are written to, or they will not be programmed.
Rev. 03 — 9 October 2009
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 68C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC68C2550B mode.
not used
INT priority bits 2 to 0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[1]
1
0
0
1
0
Receive FIFO trigger level
01
04
08
14
ISR[0]
0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
…continued
Table 11
SC68C2550B
Table
shows the data
© NXP B.V. 2009. All rights reserved.
11).
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