ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 107

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8151H–AVR–02/11
COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the
value present in the COM01:0 bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 14-2.
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting.
normal or CTC mode (non-PWM).
Table 14-3.
Mode
0
1
2
3
COM01
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
98.
WGM01
Table 14-3
However, the functionality and location of these bits are compatible with previous versions of
the timer.
(CTC0)
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
0
0
1
1
(1)
COM00
shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
0
1
0
1
WGM00
(PWM0)
0
1
0
1
(1)
Description
Normal port operation, OC0 disconnected.
Toggle OC0 on compare match
Clear OC0 on compare match
Set OC0 on compare match
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
Table 14-2
TOP
0xFF
0xFF
OCR0
0xFF
Immediate
BOTTOM
Update of
OCR0 at
TOP
Immediate
and
ATmega128A
“Modes of Operation”
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
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