ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 263

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.13.5
8151H–AVR–02/11
Scanning the Analog Comparator
Figure 24-9. Boundary-scan Cells for Oscillators and Clock Options
Figure 24-10.
Table 24-3.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported
in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-
nal capacitors to run unless the fuse is correctly programmed.
Table
Table 24-3
lators with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Scan Signals for the Oscillators
Previous
From
Cell
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TOSCK
ShiftDR
24-4.
0
1
ClockDR
summaries the scan registers for the external clock pin XTAL1, oscil-
Figure 24-12
D
UpdateDR
Q
Next
Cell
To
D
G
Q
EXTEST
is attached to each of these signals. The signals are
0
1
Clock Option
External Clock
External Crystal
External Ceramic Resonator
External RC
Low Freq. External Crystal
32kHz Timer Oscillator
XTAL1/TOSC1
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
From
Cell
ShiftDR
0
1
ClockDR
ATmega128A
Scanned Clock Line
when not Used
D
FF1
Q
Figure
next
cell
To
To System Logic
0
0
1
0
0
24-11. The
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