ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 269

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.14 ATmega128A Boundary-scan Order
8151H–AVR–02/11
Table 24-6.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Table 24-7
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is
not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
Table 24-7.
Step
6
7
8
9
10
11
Bit Number
204
203
202
201
Actions
Verify the
COMP bit
scanned out
to be 0
Verify the
COMP bit
scanned out
to be 1
shows the Scan order between TDI and TDO when the Boundary-scan Chain is
Algorithm for Using the ADC
ATmega128A Boundary-scan Order
Signal Name
AC_IDLE
ACO
ACME
AINBG
ADCEN
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x143
0x143
0x200
Figure
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
24-5, PXn. Data corresponds to FF0, PXn. Control
Module
Comparator
HOLD
1
0
1
1
1
1
PRECH
1
1
1
1
0
1
PA3.
Data
0
0
0
0
0
0
ATmega128A
hold,max
PA3.
Control
0
0
0
0
0
0
PA3.
Pullup_
Enable
0
0
0
0
0
0
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