ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 37

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8151H–AVR–02/11
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the Atmel
core. Examples of such modules are the General Purpose Register File, the Status Register and
the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from per-
forming general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.’
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
CPU
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
I/O
is halted, enabling TWI address reception in all sleep modes.
External RC
General I/O
Oscillator
modules
clk
clk
ASY
I/O
46. The clock systems are detailed below.
External clock
Control Unit
AVR Clock
Multiplexer
ADC
Clock
clk
Source clock
ADC
Reset Logic
CPU Core
clk
Oscillator
clk
Crystal
CPU
FLASH
Watchdog clock
Crystal Oscillator
Low-Frequency
RAM
Watchdog Timer
Watchdog
Oscillator
ATmega128A
“Power Manage-
Flash and
EEPROM
Calibrated RC
Oscillator
®
AVR
37
®