ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 110

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.11.5
14.11.6
8151H–AVR–02/11
TIMSK - Timer/Counter Interrupt Mask Register
TIFR - Timer/Counter Interrupt Flag Register
• Bit 2 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
• Bit 1 – OCR0UB: Output Compare Register0 Update Busy
When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set.
When OCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.
• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy
When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set.
When TCCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0,
the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary stor-
age register is read.
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFR.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
OCIE2
OCF2
R/W
R/W
7
0
7
0
TOIE2
TOV2
R/W
R/W
6
0
6
0
TICIE1
R/W
ICF1
R/W
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
4
0
4
0
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOIE1
TOV1
R/W
R/W
2
0
2
0
OCIE0
OCF0
ATmega128A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK
TIFR
110