ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 24

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.5.5
8151H–AVR–02/11
Address Latch Requirements
The control bits for the External Memory Interface are located in three registers, the MCU Con-
trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External
Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 7-6
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the External Memory Interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
octal latch (typically “74 × 573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
9 through Tables 27-16 on pages 332 - 335. The D-to-Q propagation delay (t
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
Figure 7-5.
• RD: Read strobe.
• WR: Write strobe.
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
(this figure shows the wave forms without wait-states). When ALE goes from high-to-low,
External SRAM Connected to the Atmel
h
Figure 7-5
= 5 ns. Refer to t
AVR
illustrates how to connect an external SRAM to the AVR using an
AD7:0
A15:8
ALE
WR
PD
RD
SU
).
) must not exceed address valid to ALE low (t
LAXX_LD
SU
).
TH
/t
LLAXX_ST
).
D
G
Q
in
“External Data Memory Timing”
®
AVR
®
“I/O Ports” on page
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
ATmega128A
PD
AVLLC
) must be taken
65. The XMEM
) minus PCB
Tables 27-
Fig-
24