ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 95

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5
8151H–AVR–02/11
Output Compare Unit
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC0. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter overflow (TOV0) flag is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the
output compare flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the output
compare flag generates an output compare interrupt. The OCF0 flag is automatically cleared
when the interrupt is executed. Alternatively, the OCF0 flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the WGM01:0 bits and compare output
mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for han-
dling the special cases of the extreme values in some modes of operation
on page
count
direction
clear
clk
top
bottom
DATA BUS
98).
T0
TCNTn
T0
Figure 14-3
is present or not. A CPU write overrides (has priority over) all counter clear or
T0
direction
shows a block diagram of the output compare unit.
). clk
count
clear
bottom
Increment or decrement TCNT0 by 1.
Selects between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock.
Signalizes that TCNT0 has reached maximum value.
Signalizes that TCNT0 has reached minimum value (zero).
98.
T0
Control Logic
can be generated from an external or internal clock source,
top
TOVn
(Int.Req.)
clk
Tn
Prescaler
ATmega128A
Oscillator
(“Modes of Operation”
T/C
clk
I/O
TOSC2
TOSC1
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