ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 251

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.3
8151H–AVR–02/11
TAP – Test Access Port
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port –– TAP. These pins are:
Figure 24-1. Block Diagram
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
• TCK: Test clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
• The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is
• When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
• For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is
machine.
(Scan Chains).
not provided.
TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP
input signals are internally pulled high and the JTAG is enabled for Boundary-scan and
programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG
TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or
other hardware having pull-ups (for instance the TDI-input of the next device in the scan
chain). The device is shipped with this fuse programmed.
monitored by the debugger to be able to detect External Reset sources. The debugger can
also pull the RESET pin low to reset the whole system, assuming only open collectors on the
Reset line are used in the application.
TDI
TDO
TCK
TMS
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
ADDRESS
DECODER
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
BOUNDARY SCAN CHAIN
PC
Instruction
JTAG / AVR CORE
COMMUNICATION
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
ATmega128A
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