ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 111

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.2.3
18.2.4
2548E–AVR–07/06
CADICH and CADICL – CC-ADC Instantaneous Current
CADAC3, CADAC2, CADAC1 and CADAC0 – CC-ADC Accumulate Current
The CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conver-
sion is greater than, or equal to, the compare values set by the CC-ADC Regular
Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge
Current Level, and a negative value is compared to the Regular Discharge Current Level. The
CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set
(one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling
vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.
• Bit 0 – CADICIF: CC-ADC Instantaneous Current Interrupt Flag
The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed.
The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in
SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Inter-
rupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag.
When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two
registers. CADIC15:0 represents the converted result in 2's complement format, sign extended
to 16 bits.
When CADICL is read, the CC-ADC Instantaneous Current register is not updated until CADCH
is read. Reading the registers in the sequence CADICL, CADICH will ensure that consistent val-
ues are read.
The CADAC3, CADAC2, CADAC1 and CADAC0 Registers contain the Accumulate Current
measurements in 2’s complement format, sign extended to 32 bits.
Bit
(0xE9)
(0xE8)
Bit
Read/Write
Initial Value
Bit
(0xE3)
(0xE2)
(0xE1)
(0xE0)
Read/Write
Initial Value
15
R
R
31
23
15
7
0
0
R
R
R
7
0
0
0
14
30
22
14
R
R
6
0
0
R
R
R
6
0
0
0
13
29
21
13
R
R
5
0
0
R
R
R
5
0
0
0
12
28
20
12
CADAC[31:24]
CADAC[23:16]
R
R
R
R
R
4
0
0
4
CADAC[15:8]
0
0
0
CADIC[15:8]
CADAC[7:0]
CADIC[7:0]
11
27
19
11
R
R
3
0
0
3
R
R
R
0
0
0
10
26
18
10
R
R
R
R
R
2
0
0
2
0
0
0
25
17
R
R
R
R
R
9
1
0
0
9
1
0
0
0
ATmega406
24
16
R
R
R
R
R
8
0
0
0
0
8
0
0
0
CADAC3
CADAC2
CADAC1
CADAC0
CADICH
CADICL
111