ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 219
ATmega406
Manufacturer Part Number
ATmega406
Description
Manufacturer
Atmel Corporation
Specifications of ATmega406
Flash (kbytes)
40 Kbytes
Pin Count
48
Max. Operating Frequency
1 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-30 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
2
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega406-1AAU
Manufacturer:
AT
Quantity:
20 000
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28.7.12
28.7.13
28.7.14
2548E–AVR–07/06
Programming Algorithm
Entering Programming Mode
Leaving Programming Mode
ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is
post-incremented after reading each high byte, including the first read byte. This ensures that
the first data is captured from the first address set up by PROG_COMMANDS, and reading the
last location in the page makes the program counter increment into the next page.
Figure 28-14. Flash Data Byte Register
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal
operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate
through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-
ter with sufficient number of clock pulses to complete its operation transparently for the user.
However, if too few bits are shifted between each Update-DR state during page load, the TAP
controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at
least 11 TCK cycles between each Update-DR state.
All references below of type “1a”, “1b”, and so on, refer to
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
ming Enable Register.
ming Enable Register.
TDO
TDI
D
A
A
T
Machine
State
STROBES
ADDRESS
Table
EEPROM
Lock Bits
Fuses
Flash
28-12.
ATmega406
219
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