ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 134

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.1
23.2
23.2.1
134
FET Driver
Register Description for FET Control
ATmega406
FCSR – FET Control and Status Register
Figure 23-2. Connection of external FETs
The connection of external FETs to OD, OC, and OPC is shown in
When switching on an FET, the output pulls the gate quickly low to avoid heating of the FET.
When the FET is switched completely on, the output changes operation mode in order to reduce
current consumption. The gate-source voltage for the FET when switched on,
to 13V ± 15%.
When disabling an external FET, the FET Driver output quickly pushes the gate voltage to the
source pin potential, making the gate-source voltage of the FET close to zero. This disables the
FET, and the FET Driver output switches operation mode to high impedance in order to reduce
current consumption. The external resistor will keep the gate-source voltage at zero until the
FET is enabled again and its gate is pulled low as explained above.
The FET Controller operates in a different clock domain than the CPU. Whenever a new value is
written to the FCSR, the value must be synchronized to the FET Controller clock domain. Subse-
quent writes to this register should not be made during this synchronization. Therefore, after
writing to this register, a guard time of 3 ULP Oscillator cycles + 3 CPU clock cycles is required.
It is recommended that software only reads the FCSR when handling a Battery Protection Inter-
rupt (BPINT).
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATmega406, and will always read as zero.
• Bit 5 – PWMOC: Pulse Width Modulation of OC output
Bit
(0xF0)
Read/Write
Initial Value
R
7
–
0
RN
R
6
–
0
PVT
Rdf
PWMOC
R/W
OD
5
0
PWMOPC
R/W
4
0
Rpc
OC
Rcf
CPS
R
3
0
OPC
Rpf
DFE
R/W
2
0
Figure
BATT
CFE
R/W
23-2.
1
0
+
|V
GS_ON
PFD
R/W
2548E–AVR–07/06
0
0
|
, is limited
FCSR